[PATCH v2 0/3] perf/x86: Fix perf_event_print_debug() on non-Intel PMUs

Petr Tesarik reported that reading MSR_ARCH_PERFMON_FIXED_CTR_CTRL
raises a #GP on AMD processors that support PerfMonV2, and proposed
skipping that register when no fixed counters are implemented [1].

However, perf_event_print_debug() also dumps the global control and
status registers whenever x86_pmu.version >= 2, and reads Intel
Architectural PerfMon MSRs to do so. That condition used to be
Intel-specific, but since commit 21d59e3e2c40 ("perf/x86/amd/core:
Detect PerfMonV2 support"), x86_pmu.version is also set to 2 on AMD
processors that support PerfMonV2, where none of those registers are
available.

The same reasoning therefore applies to the other registers read here,
so rather than special-casing each one or reinstating a vendor check,
this series makes the global register dump a vendor-specific operation.

[1] https://lore.kernel.org/all/[email protected]/

Previous versions can be found at
v1: https://lore.kernel.org/all/[email protected]/

Changes in v2:
  * Address build issue reported by Sashiko.
  * Use a static_call as suggested by Dapeng.
  * Pick up Tested-by from Petr.

Sandipan Das (3):
  perf/x86: Add x86_pmu::print_debug
  perf/x86: Move MSR_CORE_PERF_GLOBAL_* dump to vendor code
  perf/x86/amd: Implement x86_pmu::print_debug

 arch/x86/events/amd/core.c     | 20 ++++++++++++
 arch/x86/events/core.c         | 60 ++++++++++++++++------------------
 arch/x86/events/intel/core.c   | 32 ++++++++++++++++++
 arch/x86/events/perf_event.h   |  4 +++
 arch/x86/events/zhaoxin/core.c | 18 ++++++++++
 5 files changed, 102 insertions(+), 32 deletions(-)

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2.53.0