Re: [PATCH v5 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0
| Newsgroups | org.kernel.vger.linux-perf-users |
|---|---|
| Message-ID | <[email protected]> |
> From: Dapeng Mi <[email protected]> > > Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report. > > The L0 cache is newly added a small piece of cache which is > the closest, lowest-latency memory cache tied directly to the > execution pipeline. > > The table "Table 9-4. Data Source Field Encodings for Panther > Cove and Coyote Cove Microarchitectures" in the ISE doc chapter > "9.2.1 Panther Cove and Coyote Cove Microarchitectures Memory > Auxiliary Field Layout"[1] indicates the code "01H" means the > "L0 Hit - Minimal latency core cache hit. This request was > satisfied by the L0 data cache." > > [1]: https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html > > Assisted-by: Sashiko:gemini-3.1-pro-preview > Reviewed-by: Dapeng Mi <[email protected]> > Reviewed-by: Ian Rogers <[email protected]> > Signed-off-by: Dapeng Mi <[email protected]> > Signed-off-by: Thomas Falcon <[email protected]> Sashiko has reviewed this patch and found no issues. It looks great! -- Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2