RE: [PATCH] intel_idle: Fix C6S and C10 latency values for Pantherlake

On Tue, 2026-08-11 at 13:47 +0530, <reviewer> wrote:
> The current values are based on what I measured using wult/pbe tool.
>
> I think it will be better to explain the problem and how this patch
> fixes it, give some details about workload. And ideally, also provided
> turbostat output when it runs in parallel with the workload before and
> after this patch.

Thank you for the feedback.

Looking at other platforms in intel_idle, C-state latency values are
generally sourced from BIOS ACPI _CST characterization data. For
example, MTL-L C6 (exit_latency=140, target_residency=420) and ADL-L
C6 (exit_latency=170, target_residency=500) match their respective
ACPI _CST tables.

For PTL, I observed a discrepancy. The ACPI _CST on a Pantherlake-L
device  reports:

  C6S: latency=127us, residency=381us
  C10: latency=1048us, residency=3144us


Could you clarify which reference was used for other platforms — ACPI
_CST or wult — so we can apply a consistent methodology for PTL?

I will add the turbostat data and workload details as requested.

Thanks,
Kaushlendra