Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency
Mukesh Savaliya <[email protected]>
| Newsgroups | org.kernel.vger.linux-pm,org.infradead.lists.linux-arm-kernel,org.kernel.vger.arm-scmi,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-i2c,org.kernel.vger.linux-kernel,org.kernel.vger.linux-serial,org.kernel.vger.linux-spi |
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| Message-ID | <[email protected]> |
On 8/5/2026 1:27 AM, Praveen Talari wrote: > On the SA8255P platform there is no Linux clock handler for the SE source > clock; resources are instead managed by firmware via a genpd performance > domain. The I2C driver therefore relies on geni_se_set_rate() to apply the > fixed 19.2 MHz source clock frequency expected by the SCL divider and somewhere it's 32 MHz also and this may change too ? > counter values programmed by qcom_geni_i2c_conf(). > > Call geni_se_set_rate() directly from qcom_geni_i2c_conf() so the > configured frequency is applied to the correct device (the perf domain > device on the firmware-managed path, or se->dev otherwise) without the I2C > driver needing to know which resources_init() variant is in use. > > Drop the now-unused set_rate field from struct geni_i2c_desc, the > geni_se_set_perf_opp() usage on the SA8255P variant, and the unused freq > parameter from qcom_geni_i2c_conf(). > > Signed-off-by: Praveen Talari <[email protected]> > --- > drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index a23554d101fd..4561e2d235d5 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -213,11 +213,11 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) > return -EINVAL; > } > > -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) > +static int qcom_geni_i2c_conf(struct geni_se *se) > { > struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); > const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; > - u32 val; > + u32 val, ret; > > writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); > > @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) > itr->clk_div, itr->t_high_cnt, > itr->t_low_cnt, itr->t_cycle_cnt); > > + ret = geni_se_set_rate(&gi2c->se, 19200000); hard code ? May work currently, but if higher frequency support added, source may change. Also you have added in commit message, but add a comment also here. > + if (ret) > + return ret; > + > return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, > Bps_to_icc(gi2c->clk_freq_out)); > } [...]