[PATCH v7 6/9] dt-bindings: pwm: Document RZ/G3E GPT support
Biju <[email protected]>
| Newsgroups | org.kernel.vger.linux-pwm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-renesas-soc |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047) SoC. The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel and GPT1: 8channels). The hardware supports simultaneous control of all channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or up- and down-counter. Reviewed-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Biju Das <[email protected]> --- v6->v7: * No change. v5->v6: * No change. v4->v5: * No change. v3->v4: * No change. v2->v3: * Added Rb tag from Rob. v1->v2: * Created separate document for RZ/G3E GPT. * Updated commit header and description. --- .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml new file mode 100644 index 000000000000..cb4ffab5f47f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E General PWM Timer (GPT) + +maintainers: + - Biju Das <[email protected]> + +description: | + RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit + timer. It supports the following functions + * 32 bits x 16 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Four I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to a maximum of 8 ELC events. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to the status of two input pins. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by detected short-circuits between output + pins. + * A/D converter start triggers can be generated. + * Compare match A to F event and overflow/underflow event can be output + to the ELC. + * Enables the noise filter for input capture. + * Logical operation between the channel output. + +properties: + compatible: + items: + - const: renesas,r9a09g047-gpt # RZ/G3E + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.0 + - description: Compare match with the GTCCRC for channel GPT{0,1}.0 + - description: Compare match with the GTCCRD for channel GPT{0,1}.0 + - description: Compare match with the GTCCRE for channel GPT{0,1}.0 + - description: Compare match with the GTCCRF for channel GPT{0,1}.0 + - description: A and B both high interrupt for channel GPT{0,1}.0 + - description: A and B both low interrupt for channel GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.1 + - description: Compare match with the GTCCRC for channel GPT{0,1}.1 + - description: Compare match with the GTCCRD for channel GPT{0,1}.1 + - description: Compare match with the GTCCRE for channel GPT{0,1}.1 + - description: Compare match with the GTCCRF for channel GPT{0,1}.1 + - description: A and B both high interrupt for channel GPT{0,1}.1 + - description: A and B both low interrupt for channel GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.2 + - description: Compare match with the GTCCRC for channel GPT{0,1}.2 + - description: Compare match with the GTCCRD for channel GPT{0,1}.2 + - description: Compare match with the GTCCRE for channel GPT{0,1}.2 + - description: Compare match with the GTCCRF for channel GPT{0,1}.2 + - description: A and B both high interrupt for channel GPT{0,1}.2 + - description: A and B both low interrupt for channel GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.3 + - description: Compare match with the GTCCRC for channel GPT{0,1}.3 + - description: Compare match with the GTCCRD for channel GPT{0,1}.3 + - description: Compare match with the GTCCRE for channel GPT{0,1}.3 + - description: Compare match with the GTCCRF for channel GPT{0,1}.3 + - description: A and B both high interrupt for channel GPT{0,1}.3 + - description: A and B both low interrupt for channel GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.4 + - description: Compare match with the GTCCRC for channel GPT{0,1}.4 + - description: Compare match with the GTCCRD for channel GPT{0,1}.4 + - description: Compare match with the GTCCRE for channel GPT{0,1}.4 + - description: Compare match with the GTCCRF for channel GPT{0,1}.4 + - description: A and B both high interrupt for channel GPT{0,1}.4 + - description: A and B both low interrupt for channel GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.5 + - description: Compare match with the GTCCRC for channel GPT{0,1}.5 + - description: Compare match with the GTCCRD for channel GPT{0,1}.5 + - description: Compare match with the GTCCRE for channel GPT{0,1}.5 + - description: Compare match with the GTCCRF for channel GPT{0,1}.5 + - description: A and B both high interrupt for channel GPT{0,1}.5 + - description: A and B both low interrupt for channel GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.6 + - description: Compare match with the GTCCRC for channel GPT{0,1}.6 + - description: Compare match with the GTCCRD for channel GPT{0,1}.6 + - description: Compare match with the GTCCRE for channel GPT{0,1}.6 + - description: Compare match with the GTCCRF for channel GPT{0,1}.6 + - description: A and B both high interrupt for channel GPT{0,1}.6 + - description: A and B both low interrupt for channel GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.7 + - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.7 + - description: Compare match with the GTCCRC for channel GPT{0,1}.7 + - description: Compare match with the GTCCRD for channel GPT{0,1}.7 + - description: Compare match with the GTCCRE for channel GPT{0,1}.7 + - description: Compare match with the GTCCRF for channel GPT{0,1}.7 + - description: A and B both high interrupt for channel GPT{0,1}.7 + - description: A and B both low interrupt for channel GPT{0,1}.7 + + interrupt-names: + items: + - const: gtcia0 + - const: gtcib0 + - const: gtcic0 + - const: gtcid0 + - const: gtcie0 + - const: gtcif0 + - const: gtcih0 + - const: gtcil0 + - const: gtcia1 + - const: gtcib1 + - const: gtcic1 + - const: gtcid1 + - const: gtcie1 + - const: gtcif1 + - const: gtcih1 + - const: gtcil1 + - const: gtcia2 + - const: gtcib2 + - const: gtcic2 + - const: gtcid2 + - const: gtcie2 + - const: gtcif2 + - const: gtcih2 + - const: gtcil2 + - const: gtcia3 + - const: gtcib3 + - const: gtcic3 + - const: gtcid3 + - const: gtcie3 + - const: gtcif3 + - const: gtcih3 + - const: gtcil3 + - const: gtcia4 + - const: gtcib4 + - const: gtcic4 + - const: gtcid4 + - const: gtcie4 + - const: gtcif4 + - const: gtcih4 + - const: gtcil4 + - const: gtcia5 + - const: gtcib5 + - const: gtcic5 + - const: gtcid5 + - const: gtcie5 + - const: gtcif5 + - const: gtcih5 + - const: gtcil5 + - const: gtcia6 + - const: gtcib6 + - const: gtcic6 + - const: gtcid6 + - const: gtcie6 + - const: gtcif6 + - const: gtcih6 + - const: gtcil6 + - const: gtcia7 + - const: gtcib7 + - const: gtcic7 + - const: gtcid7 + - const: gtcie7 + - const: gtcif7 + - const: gtcih7 + - const: gtcil7 + + clocks: + items: + - description: Core clock (PCLKD) + - description: Bus clock (PCLKA) + + clock-names: + items: + - const: core + - const: bus + + power-domains: + maxItems: 1 + + resets: + items: + - description: Reset for bus clock (PCLKA/PCLKD) + - description: Reset for core clock (PCLKD) + + reset-names: + items: + - const: rst_p + - const: rst_s + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pwm@13010000 { + compatible = "renesas,r9a09g047-gpt"; + reg = <0x13010000 0x10000>; + interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; + clock-names = "core", "bus"; + power-domains = <&cpg>; + resets = <&cpg 0x59>, <&cpg 0x5a>; + reset-names = "rst_p", "rst_s"; + #pwm-cells = <3>; + }; -- 2.43.0