Re: [PATCH 2/6] raid6: add missing vzeroupper to AVX2 code

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing vzeroupper in AVX-512 RAID6 code leading to severe AVX-SSE transition penalties
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--- Patch [2]: [PATCH 2/6] raid6: add missing vzeroupper to AVX2 code ---
commit 053e34bcf70317a18a7c9c774075bd7eb1c95140
Author: Eric Biggers <[email protected]>

raid6: add missing vzeroupper to AVX2 code

Since the AVX2 optimized RAID6 code uses YMM registers, execute vzeroupper
before returning from it. This is needed to avoid degrading the performance
of any later SSE code that may happen to be executed.

> diff --git a/lib/raid/raid6/x86/avx2.c b/lib/raid/raid6/x86/avx2.c
> index 7d829c669ea79..3cc2fe7ac42c5 100644
> --- a/lib/raid/raid6/x86/avx2.c
> +++ b/lib/raid/raid6/x86/avx2.c
> @@ -67,6 +67,7 @@ static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
>  	}
>  
>  	asm volatile("sfence" : : : "memory");
> +	asm volatile("vzeroupper");

[Severity: High]
This is a pre-existing issue, but does the AVX-512 RAID6 code also need this
fix?

Like the AVX2 code, the AVX-512 code uses ZMM registers but returns without
executing vzeroupper before kernel_fpu_end().

For example, in lib/raid/raid6/x86/avx512.c:raid6_avx5121_gen_syndrome():

        asm volatile("sfence" : : : "memory");
        kernel_fpu_end();
}

And similarly in lib/raid/raid6/x86/recov_avx512.c:raid6_2data_recov_avx512().

Would omitting vzeroupper here leave the upper bits of ZMM registers dirty
and incur severe AVX-SSE transition penalties if the CPU subsequently
executes legacy SSE code, causing a performance regression?

>  	kernel_fpu_end();
>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2