Re: [PATCH 0/6] x86: add missing vzeroupper instructions

On Mon, Aug 17, 2026 at 11:55:23AM +0100, David Laight wrote:
> On Mon, 17 Aug 2026 02:15:19 -0700
> Christoph Hellwig <[email protected]> wrote:
> 
> > On Sun, Aug 16, 2026 at 10:31:59AM -0700, Eric Biggers wrote:
> > > As for kernel_fpu_begin(), no, it doesn't do vzeroupper.
> > > 
> > > I do think that some years down the line, we'll drop the use of SSE in
> > > the kernel entirely.  At that point, vzeroupper in kernel_fpu_end()
> > > would make sense.  
> > 
> > Or add kernel_avx_{begin,end} wrappers that include the vzeroupper
> > in kernel_avx_end.  That would be a lot easier to use than the manual
> > vzeroupper in every modern user of in-kernel AVX.
> > 
> 
> You might want one in the start as well.
> I have a theory that the avx512 logic was added as a completely separate block.
> This meant it could be included in cpu for testing but disabled in any
> released to customers.
> (Or maybe the it is the original avx logic that used latches not in the
> normal register file.)
> A side effect is that different latches are used for the low bits of the
> registers - so when you change to/from avx512 the register contents have to
> be transferred between the blocks - adding latency.
> So if the wrong registers are live for the code you are going to execute
> the data has to be transferred across.
> 
> There are also other effects as well.
> I found this link: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html
> It is a few years old now (2020) but probably still relevant.
> A quick summary is that the first 256 or 512 bit instruction starts a 9us
> window where the cpu runs at 1/4 speed, for 512 bit that is followed by 11us
> where nothing happens at all. 

The linked article is about Skylake, which is an older Intel CPU that
has a bad AVX-512 implementation with overly-eager downclocking.  Later
Intel CPUs improved the implementation.  And of course, AMD just
implemented it properly from the start without the downclocking issues.
Information about AMD Zen 5's AVX-512 implementation can be found here:
https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/

Most of the AVX-512 optimized code in the kernel already requires
!X86_FEATURE_PREFER_YMM, excluding Skylake as well as Ice Lake.

That being said, if I recall correctly, even with Intel's improved
implementation on Sapphire Rapids and Emerald Rapids, Intel does still
have some start-up latency for accessing ZMM registers.  AMD doesn't.  I
don't believe vzeroupper helps, unfortunately.

I've considered setting X86_FEATURE_PREFER_YMM on all Intel CPUs, but
then even workloads that would benefit from ZMM registers wouldn't use
them.  And I suspect the Intel folks wouldn't agree with that either.

- Eric