Re: [PATCH 07/16] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3L SoC

Krzysztof Kozlowski <[email protected]>
Newsgroups org.kernel.vger.linux-renesas-soc,org.freedesktop.lists.dri-devel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel
Message-ID <20260708-satisfied-mammoth-from-betelgeuse-d4fe94@quoll>
On Sat, Jul 04, 2026 at 10:34:17AM +0100, Biju wrote:
>        model-dependent. Each port shall have a single endpoint.
>  
>      patternProperties:
> -      "^port@[0-1]$":
> +      "^port@[0-2]$":
>          $ref: /schemas/graph.yaml#/properties/port
>          unevaluatedProperties: false
>  
> @@ -88,7 +89,6 @@ required:
>    - clocks
>    - clock-names
>    - power-domains
> -  - ports

Why doing this change?

>    - renesas,vsps
>  
>  additionalProperties: false
> @@ -108,6 +108,7 @@ allOf:
>              port@0:
>                description: DPI
>              port@1: false
> +            port@2: false

Best regards,
Krzysztof
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