[PATCH v2 2/2] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe
Prabhakar <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Lad Prabhakar <[email protected]> Enable the PCIE1 slot which is connected to PCIe0 channel. Signed-off-by: Lad Prabhakar <[email protected]> --- v1->v2: - Renamed the node name from pcie to pcie0. --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 3c1ddacc0944..637fc92dcc26 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -384,6 +384,18 @@ &ostm7 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + num-lanes = <4>; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -430,6 +442,12 @@ i2c8_pins: i2c8 { <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ }; + pcie0_pins: pcie0 { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; -- 2.54.0