Re: (subset) [PATCH v4 0/5] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS
Marek Vasut <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-doc,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
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| Message-ID | <[email protected]> |
On 7/9/26 2:59 PM, Manivannan Sadhasivam wrote: > On Thu, Jul 09, 2026 at 02:57:47PM +0200, Manivannan Sadhasivam wrote: >> >> On Tue, 07 Jul 2026 22:35:38 +0200, Marek Vasut wrote: >>> Configure all R-Car Gen4 PCIe controller MSI registers fully, both in >>> case MSI are enabled and disabled. >>> >>> Patch GIC ITS driver and add quirks for R-Car Gen4 GIC ITS, which is >>> configured to 32-bit address width for AXI or APB interface. >>> >>> Switch R-Car V4H to use GIC ITS in its DT and describe the GIC ITS >>> implementation cacheable and shareable limitations. >>> >>> [...] >> >> Applied, thanks! >> >> [3/5] irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling >> commit: 96b193897fd374fcb63a782c52f8b079134d0222 >> [4/5] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround >> commit: 14e8394423ffd4fd28884ec8b4d5ba15be6e7e0d > > B4 got confused here. I applied all 4 patches. Understood. 5/5 should go through Geert / Renesas SoC tree ? Thank you !