RE: [PATCH v19 06/12] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag

Hi All,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: 09 July 2026 20:29
> Subject: [PATCH v19 06/12] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag
> 
> From: Biju Das <[email protected]>
> 
> The RZ/G3L SoC integrates a fixed internal /2 clock divider that is active across all bus timing modes
> except for HS400.
> 
> Introduce a new feature flag, TMIO_MMC_INTERNAL_DIVIDER (bit 14), inside the TMIO platform headers to
> mark hardware profiles carrying this integrated divider scheme.
> 
> Modify renesas_sdhi_clk_update() to inspect this flag when setting and reporting clock rates. When the
> flag is set, the function bypasses the standard base division logic via a modified clkh_shift adjustment,
> then factors the physical /2 division step directly into the final calculated frequency value, provided
> the current bus timing is not MMC_TIMING_MMC_HS400.
> 
> As no existing platforms configure this newly introduced bitmask flag, this patch delivers the underlying
> operational infrastructure with zero functional impact on existing supported chip variants.
> 
> Signed-off-by: Biju Das <[email protected]>
> ---
> v18->v19:
>  * Updated commit description.
>  * Dropped divider variable from struct renesas_sdhi.
>  * Updated renesas_sdhi_clk_update() to return rate for HS400mode
>    and nonHS400mode(uses 1/2 internal divider).
> v18:
>  * New patch using flag.
> ---
>  drivers/mmc/host/renesas_sdhi_core.c | 13 +++++++++++--
>  include/linux/platform_data/tmio.h   |  3 +++
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> index 832a7a7be725..b6bba03316fe 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -184,10 +184,19 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
> 
>  	clk_set_rate(ref_clk, best_freq);
> 
> -	if (priv->clkh)
> +	if (priv->clkh) {
> +		if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER)
> +			clkh_shift = 1;
> +
>  		clk_set_rate(priv->clk, best_freq >> clkh_shift);
> +	}
> +
> +	freq = clk_get_rate(priv->clk);
> +	if ((host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER) &&
> +	    host->mmc->ios.timing != MMC_TIMING_MMC_HS400)
> +		freq /= 2;


Looks sashiko's feedback is false positive as it is preparatory patch
and there is no platform uses TMIO_MMC_INTERNAL_DIVIDER. Moreover
the check is for early SoCs that do not support tuning.

[1] https://sashiko.dev/#/patchset/20260709192916.630794-1-biju.das.jz%40bp.renesas.com

Cheers,
Biju

> 
> -	return clk_get_rate(priv->clk);
> +	return freq;
>  }
> 
>  static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, diff --git
> a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h
> index 868a21842fa5..6c512e96e192 100644
> --- a/include/linux/platform_data/tmio.h
> +++ b/include/linux/platform_data/tmio.h
> @@ -53,6 +53,9 @@
>  /* Some controllers have tuning delay */
>  #define TMIO_MMC_TUNING_DELAY		BIT(13)
> 
> +/* Some controllers have internal divider */
> +#define TMIO_MMC_INTERNAL_DIVIDER	BIT(14)
> +
>  struct tmio_mmc_data {
>  	void				*chan_priv_tx;
>  	void				*chan_priv_rx;
> --
> 2.43.0