Re: [PATCH 5/6] clk: renesas: r9a08g046-cpg: Add MIPI DSI and LCDC clock/reset entries

Hi Biju,

Thanks for your patch!

s/r9a08g046-cpg/r9a08g046/

On Fri, 19 Jun 2026 at 18:40, Biju <[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Add clock and reset entries for the MIPI DSI and LCDC peripherals on the
> RZ/G3L (R9A08G046) SoC.
>
> Signed-off-by: Biju Das <[email protected]>
> ---
>  drivers/clk/renesas/r9a08g046-cpg.c | 62 +++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> index 4488bd1988e8..7cea2c6d2c42 100644
> --- a/drivers/clk/renesas/r9a08g046-cpg.c
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> @@ -19,22 +19,26 @@
>  #define G3L_CPG_PL3_DDIV               (0x208)
>  #define G3L_CPG_SDHI_DDIV              (0x218)
>  #define G3L_CPG_GE3D_DDIV              (0x224)
> +#define G3L_CPG_DSI_DDIV               (0x228)
>  #define G3L_CPG_CA55CORE_DDIV          (0x234)
>  #define G3L_CPG_RSCI_DDIV              (0x238)
>  #define G3L_CPG_RSPI_DDIV              (0x23c)
>  #define G3L_CPG_SDHI_DSEL              (0x244)
>  #define G3L_CLKDIVSTATUS               (0x280)
>  #define G3L_CLKSELSTATUS               (0x284)
> +#define G3L_CPG_DSI_SSEL               (0x408)
>  #define G3L_CPG_GE3D_SSEL              (0x40c)
>  #define G3L_CPG_ETH_SSEL               (0x410)
>  #define G3L_CPG_RSCI_SSEL              (0x414)
>  #define G3L_CPG_RSPI_SSEL              (0x418)
> +#define G3L_CPG_DSI_SDIV               (0x430)
>  #define G3L_CPG_ETH_SDIV               (0x434)
>
>  /* RZ/G3L Specific division configuration.  */
>  #define G3L_DIVPL2A            DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
>  #define G3L_DIVPL2B            DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
>  #define G3L_DIVPL3A            DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
> +#define G3L_DIVPL3B            DDIV_PACK(G3L_CPG_PL3_DDIV, 4, 2)
>  #define G3L_DIV_SDHI0          DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2)
>  #define G3L_DIV_SDHI1          DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2)
>  #define G3L_DIV_SDHI2          DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2)
> @@ -54,11 +58,14 @@
>  #define G3L_SDIV_ETH_B         DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
>  #define G3L_SDIV_ETH_C         DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
>  #define G3L_SDIV_ETH_D         DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1)
> +#define G3L_SDIV_DSI_C_SET     DDIV_PACK(G3L_CPG_DSI_SDIV, 8, 1)
> +#define G3L_DIV_DSI            DDIV_PACK(G3L_CPG_DSI_DDIV, 0, 2)

Please preserve sort order for both newly-added lines.

>
>  /* RZ/G3L Clock status configuration. */
>  #define G3L_DIVPL2A_STS                DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
>  #define G3L_DIVPL2B_STS                DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
>  #define G3L_DIVPL3A_STS                DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
> +#define G3L_DIVPL3B_STS                DDIV_PACK(G3L_CLKDIVSTATUS, 9, 1)
>  #define G3L_DIV_CA55_CORE0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 12, 1)
>  #define G3L_DIV_CA55_CORE1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 13, 1)
>  #define G3L_DIV_CA55_CORE2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 14, 1)
> @@ -78,6 +85,7 @@
>  #define G3L_SEL_SDHI1_STS      SEL_PLL_PACK(G3L_CLKSELSTATUS, 17, 1)
>  #define G3L_SEL_SDHI2_STS      SEL_PLL_PACK(G3L_CLKSELSTATUS, 18, 1)
>  #define G3L_DIV_GE3D_STS       DDIV_PACK(G3L_CLKDIVSTATUS, 27, 1)
> +#define G3L_DIV_DSI_STS                DDIV_PACK(G3L_CLKDIVSTATUS, 28, 1)
>
>  /* RZ/G3L Specific clocks select. */
>  #define G3L_SEL_SDHI0          SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 0, 2)
> @@ -101,6 +109,7 @@
>  #define G3L_SEL_RSPI0          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)
>  #define G3L_SEL_RSPI1          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)
>  #define G3L_SEL_RSPI2          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)
> +#define G3L_SEL_DSI            SEL_PLL_PACK(G3L_CPG_DSI_SSEL, 0, 1)

Sort order?

> @@ -347,6 +388,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
>         DEF_G3S_DIV("G", R9A08G046_CLK_G, CLK_SEL_GE3D, G3L_DIV_GE3D, G3L_DIV_GE3D_STS,
>                     dtable_1_32, 0, 0, 0, NULL),
>         DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1),
> +       DEF_FIXED("dsi_pllclk", R9A08G046_MIPI_DSI_PLLCLK, R9A08G046_CLK_M4, 1, 1),

"mipi_dsi_pllclk"

>  };
>
>  static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
> @@ -400,6 +442,22 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
>                                         MSTOP(BUS_PERI_VIDEO, BIT(12))),
>         DEF_MOD("ge3d_ace_clk",         R9A08G046_GE3D_ACE_CLK, R9A08G046_CLK_P1, 0x558, 2,
>                                         MSTOP(BUS_PERI_VIDEO, BIT(12))),
> +       DEF_MOD("dsi_sysclk",           R9A08G046_MIPI_DSI_SYSCLK, R9A08G046_CLK_M5, 0x568, 1,

"mipi_dsi_sysclk"

> +                                       MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))),
> +       DEF_MOD("dsi_aclk",             R9A08G046_MIPI_DSI_ACLK, R9A08G046_CLK_P1, 0x568, 2,

"mipi_dsi_aclk"

> +                                       MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))),
> +       DEF_MOD("dsi_pclk",             R9A08G046_MIPI_DSI_PCLK, R9A08G046_CLK_P2, 0x568, 3,

"mipi_dsi_pclk"

> +                                       MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))),
> +       DEF_MOD("dsi_vclk",             R9A08G046_MIPI_DSI_VCLK, R9A08G046_CLK_M3, 0x568, 4,

"mipi_dsi_vclk"

> +                                       MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))),
> +       DEF_MOD("dsi_lpclk",            R9A08G046_MIPI_DSI_LPCLK, R9A08G046_CLK_M1, 0x568, 5,

"mipi_dsi_lpclk"


> +                                       MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))),
> +       DEF_MOD("lcdc_clk_a",           R9A08G046_LCDC_CLK_A, R9A08G046_CLK_P1, 0x56c, 0,
> +                                       MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))),
> +       DEF_MOD("lcdc_clk_d",           R9A08G046_LCDC_CLK_D, R9A08G046_CLK_M3, 0x56c, 1,
> +                                       MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))),
> +       DEF_MOD("lcdc_clk_p",           R9A08G046_LCDC_CLK_P, R9A08G046_CLK_P2, 0x56c, 2,
> +                                       MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))),
>         DEF_MOD("ssi0_pclk2",           R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0,
>                                         MSTOP(BUS_MCPU1, BIT(10))),
>         DEF_MOD("ssi0_pclk_sfr",        R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 1,

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds