[PATCH v3 7/8] arm64: dts: renesas: r9a08g045: Add CAN-FD node
Claudiu Beznea <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-can,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Claudiu Beznea <[email protected]> The Renesas RZ/G3S SoC includes a CAN-FD controller with two channels. Add the corresponding device tree node. Reviewed-by: Biju Das <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> --- Changes in v3: - none Changes in v2: - collected tags arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 3a69bb246bab..fe46f3d9c7cc 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -29,6 +29,13 @@ audio_clk2: audio2-clk { clock-frequency = <0>; }; + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -498,6 +505,38 @@ ssi3: ssi@100a8c00 { status = "disabled"; }; + canfd: can@100c0000 { + compatible = "renesas,r9a08g045-canfd"; + reg = <0 0x100c0000 0 0x20000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A08G045_CANFD_PCLK>, + <&cpg CPG_MOD R9A08G045_CANFD_CLK_RAM>, + <&can_clk>; + clock-names = "fck", "ram_clk", "can_clk"; + resets = <&cpg R9A08G045_CANFD_RSTP_N>, + <&cpg R9A08G045_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; -- 2.43.0