[GIT PULL] clk: renesas: Updates for v7.3

	Hi Mike, Stephen,

The following changes since commit dc59e4fea9d83f03bad6bddf3fa2e52491777482:

  Linux 7.2-rc1 (2026-06-28 12:01:31 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v7.3-tag1

for you to fetch changes up to 2df26b8663b6f315d0e9364927c8503280fe3dd3:

  clk: r9a08g045: Add clocks and resets for CAN-FD (2026-07-13 13:58:01 +0200)

----------------------------------------------------------------
clk: renesas: Updates for v7.3

  - Add RTC and display clocks on RZ/T2H and RZ/N2H,
  - Add audio and display clocks and resets on RZ/G3E,
  - Add SDHI, GPU, and USB2.0 clocks and resets on RZ/G3L,
  - Update the maintainer for the VersaClock 7 driver,
  - Add CAN-FD clocks and resets for RZ/G3S.
  - Miscellaneous fixes and improvements.

Note that this includes DT binding definition updates for the RZ/T2H and
RZ/N2H SoCs, which are shared by the clock subsystem and DT source
files.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (4):
      clk: renesas: r9a08g046: Add clock and reset entries for SDHI
      clk: renesas: r9a08g046: Add clock and reset entries for GE3D
      clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
      dt-bindings: clock: renesas,versaclock7: Update maintainer

Claudiu Beznea (1):
      clk: r9a08g045: Add clocks and resets for CAN-FD

Geert Uytterhoeven (1):
      Merge tag 'renesas-r9a09g077-dt-binding-defs-tag7' into renesas-clk-for-v7.3

John Madieu (2):
      dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
      clk: renesas: r9a09g047: Add audio clock and reset support

Lad Prabhakar (7):
      dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID
      dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
      clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
      clk: renesas: r9a09g077: Add RTC clocks
      clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
      clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
      clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline

Tommaso Merciai (1):
      clk: renesas: r9a09g047: Add LVDS clocks and resets

 .../bindings/clock/renesas,rzv2h-cpg.yaml          |   6 +
 .../bindings/clock/renesas,versaclock7.yaml        |   2 +-
 MAINTAINERS                                        |   6 +-
 drivers/clk/renesas/Kconfig                        |   6 +
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r9a08g045-cpg.c                |   9 +
 drivers/clk/renesas/r9a08g046-cpg.c                | 130 +++++++
 drivers/clk/renesas/r9a09g047-cpg.c                | 123 ++++++-
 drivers/clk/renesas/r9a09g077-cpg.c                | 375 ++++++++++++++++++++-
 drivers/clk/renesas/renesas-cpg-mssr.c             |  20 +-
 drivers/clk/renesas/rzv2h-cpg-lib.c                | 217 ++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c                    | 203 -----------
 .../dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h |   2 +
 .../dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h |   2 +
 include/linux/clk/renesas.h                        |  34 +-
 15 files changed, 913 insertions(+), 223 deletions(-)
 create mode 100644 drivers/clk/renesas/rzv2h-cpg-lib.c

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds