RE: [PATCH 0/3] soc: renesas: rz-sysc: Add RZ/G3L PWRRDY power sequencing support

Hi All,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: 25 July 2026 13:34
> Subject: [PATCH 0/3] soc: renesas: rz-sysc: Add RZ/G3L PWRRDY power sequencing support
> 
> From: Biju Das <[email protected]>
> 
> Hi all,
> 
> Some RZ SoCs (e.g. RZ/G3L) have a PWRRDY register that signals power readiness for various IPs (USB, DSI,
> CSI, etc.) to their respective controllers. This register is part of the SYSC IP. Add a dedicated power
> sequencing driver to handle these signals.
> 
> This series adds that support:
> 
> - Patch 1 adds a pwrrdy_pwrseq flag to struct rz_sysc_soc_id_init_data,
>   sets it for RZ/G3L, and has the SYSC driver register a
>   "pwrseq-pwrrdy" auxiliary device when the flag is set, so a
>   dedicated driver can bind to it and handle the sequencing.
> 
> - Patch 2 adds that dedicated driver, pwrseq-renesas-pwrrdy, which
>   binds to the auxiliary device exposed by patch 1 and exposes
>   usb-pwrrdy, dsi-pwrrdy, and csi-pwrrdy pwrseq targets, toggling the
>   appropriate bits in the SYS_PWRRDY_N register via the parent SYSC
>   driver's regmap.
> 
> - Patch 3 selects POWER_SEQUENCING_RENESAS_PWRRDY from
>   SYSC_R9A08G046 so the new driver is built whenever RZ/G3L SYSC
>   support is enabled.
> 
> This series is based on proposal for power sequence driver [1] for USB PWRRDY signal and DSI PWRRDY
> signal[2].
> 
> I will send USB/DSI/CSI driver patches based on this series soon.
> 
>  [1] https://lore.kernel.org/all/CAPDyKFpLnREr4C=wZ7o8Lb-CZbQa4Nr2VTuYdZHZ26Rcb1Masg@mail.gmail.com/

Please find the link for original proposal for power sequence driver

https://lore.kernel.org/all/[email protected]/#t

Cheers,
Biju