Re: [PATCH v2 01/16] dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L

Krzysztof Kozlowski <[email protected]> Mon, 3 Aug 2026 10:34:07 +0200

Newsgroups	org.kernel.vger.linux-renesas-soc,org.freedesktop.lists.dri-devel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel
Message-ID	<20260803-prodigious-brave-myna-08deb7@quoll>

On Wed, Jul 29, 2026 at 01:54:53PM +0100, Biju wrote:
> From: Biju Das <[email protected]>
> 
> The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY
> timings and also the PLLCLK is ungateble clock. Add the compatible
> string "renesas,r9a08g046-mipi-dsi" to handle these difference for the
> Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block.
> Document renesas,sysc-pwrrdy property to handle the power control.
> 
> Signed-off-by: Biju Das <[email protected]>
> ---
> v1->v2:
>  * Dropped renesas,sysc-pwrrdy property as it is modelled as power
>    sequence.
> ---
>  .../devicetree/bindings/display/bridge/renesas,dsi.yaml          | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof