Re: [PATCH v4 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers

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On Tue, Jul 21, 2026 at 10:29:48AM +0200, Herve Codina (Schneider Electric)=
 wrote:
> The Renesas RZ/N1 timer block controller is the controller in charge of
> timers available in the Renesas RZ/N1 SoCs family.
>=20
> This controller handles 8 timers:
>   - 6 16-bit timers
>   - 2 32-bit timers
>=20
> Each timer has its own interrupt, its own prescaler that can be used to
> divide the clock by 25 and all of them can work in either one-shot or
> periodic mode.
>=20
> Signed-off-by: Herve Codina (Schneider Electric) <[email protected]=
m>

Dunno how much this helps, but I successfully ran 'inconsistency-check',
'nanosleep', and 'clocksource-switch' from the kernel selftest on my N1D
board.

Tested-by: Wolfram Sang <[email protected]>


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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmpyS/MACgkQFA3kzBSg
KbYG7Q/9GR7b28yQC0ny+ZFY3WtMlhWKPoOvjOFZ5GjiCbaNgc4fYoDmEXpgaLya
3vX5Z7/F5okVIlk5VqsvzIood8yL1Jo6baOZlW5YZVt5WtVLeW7pnmxAEvgrKBiM
p55UX1qDXPaLpVux4jT5GWEwgrcJTKgEm+ry/Ami4DRg+i3Aah2gn7Nj67Zu1c2Z
JVGtcBZwLEBRj6Tunr+62fDXpSKgtefGWGbIMA8o7kfeIvdjz/oaAcrx0/eNB1wN
jnf8ob7HuzWq1qHVAUhUufNU6qLpYU5miCop2saTIeA1L7/mkh68OIZk+RJ/2m2T
MTOP9xbKkM3Inpq8YfL0KRMCZs6KidghbmAypccrAKKZj/BXAKtASm0nRsot+V1V
IDgeqTtGmGcK3ovwlWE5Z86IboOFbOUxJJcfLhFLJ1Sg9Hjnmbr+wJ0+e3eJr7ZA
kEXrI2JZXAdzwKiHsNHc4aF3opfK11EYO2WeKIpN26SnfGXZyyp0nYtteQZEKKVf
DUkpUWmXD5BEQjmciCSCy1cAz/YhWbdTiDItE7v8w0wyYfiaFnhh5gKr6aP6sWE0
wDN4xbabh8rPv3ucJSme/DtnecrBKs/5smDWm2LnNLUgw4p3mUe4CNTl0KnOUW91
h2lYwiGp1yxLtwvwVJtATrbwB2VzV2VBDC56sBTjq3/Fvi1mV+8=
=03fo
-----END PGP SIGNATURE-----

--pV0yin9mZAw4oQrG--