RE: [PATCH v2 09/16] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

Hi,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: 29 July 2026 13:55
> Subject: [PATCH v2 09/16] dt-bindings: display: bridge: Document Renesas =
RZ/G3L LVDS encoder
>=20
> From: Biju Das <[email protected]>
>=20
> Document the LVDS encoder IP found on the RZ/G3L SoC. It supports single-=
link mode. LVDS and the DSI
> interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal=
. However, the LVDS module
> cannot be used at the same time as MIPI-DSI.
>=20
> Signed-off-by: Tommaso Merciai <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Biju Das <[email protected]>
> ---
> v1->v2:
>  * No change.
> v5[1]->v1:
>  * No change.
> v5 [1] https://lore.kernel.org/all/20260625172359.292631-2-biju.das.jz@bp=
.renesas.com/#t
> v4->v5:
>  * Collected tag.
> v3->v4:
>  * Dropped the tags as it is a rework dropping parent node that contains
>    simple-mfd and syscon.
> v2->v3:
>  * Collected tag.
> v2->v2[1]:
>  * No change.
> [1] https://lore.kernel.org/all/[email protected]=
rg/
> v1->v2:
>  * Collected tag.
> ---
>  .../bridge/renesas,r9a08g046-lvds.yaml        | 120 ++++++++++++++++++
>  1 file changed, 120 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/rene=
sas,r9a08g046-lvds.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a=
08g046-lvds.yaml
> b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds=
.yaml
> new file mode 100644
> index 000000000000..4cd7b688fbf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046
> +++ -lvds.yaml
> @@ -0,0 +1,120 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id:
> +http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yam
> +l#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3L LVDS Encoder
> +
> +maintainers:
> +  - Biju Das <[email protected]>
> +  - Tommaso Merciai <[email protected]>
> +
> +description: |
> +  This binding describes the LVDS encoder embedded in the Renesas
> +RZ/G3L
> +  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
> +  (Data) + 1 lane (Clock).
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a08g046-lvds
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Peripheral clock
> +      - description: PHY clock
> +      - description: Dot clock
> +
> +  clock-names:
> +    items:
> +      - const: pclk
> +      - const: phyclk
> +      - const: dotclk
> +
> +  resets:
> +    items:
> +      - description: LVDS_RESET_N
> +      - description: MIPI_DSI_PRESET_N
> +      - description: MIPI_DSI_CMN_RSTB
> +      - description: MIPI_DSI_ARESET_N
> +
> +  reset-names:
> +    items:
> +      - const: lvdrst
> +      - const: prst
> +      - const: rst
> +      - const: arst
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: Input channel, directly connected to the Display Un=
it.
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: |
> +          Output channel, directly connected to the LVDS panel or bridge=
.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> +    lvds@108a0000 {
> +        compatible =3D "renesas,r9a08g046-lvds";
> +        reg =3D <0x108a0000 0x10000>;
> +        clocks =3D <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +                 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> +                 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> +        clock-names =3D "pclk", "phyclk", "dotclk";
> +        resets =3D <&cpg R9A08G046_LVDS_RESET_N>,
> +                 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> +                 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +                 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> +        reset-names =3D "lvdrst", "prst", "rst", "arst";
> +        power-domains =3D <&cpg>;
> +
> +        ports {
> +            #address-cells =3D <1>;
> +            #size-cells =3D <0>;
> +
> +            port@0 {
> +                reg =3D <0>;
> +                lvds0_in: endpoint {
> +                    remote-endpoint =3D <&du_out_lvds0>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg =3D <1>;
> +                lvds0_out: endpoint {
> +                    remote-endpoint =3D <&panel_in>;
> +                };
> +            };
> +        };
> +    };
> +...
> --
> 2.43.0

Applied to drm-misc/next.

Cheers,
Biju