Re: [PATCH 1/2] arm64: dts: renesas: cat875: Specify ethernet PHY reset timings
Geert Uytterhoeven <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <CAMuHMdWvPtnH0WUjp1+jTn=K9=RCydq8_O2Ri+FfedcanRWV8g@mail.gmail.com> |
On Tue, 14 Jul 2026 at 15:05, Marek Vasut <[email protected]> wrote: > The RTL8211E reference manual [1] page 38 chapter 7.16. PHY Reset > (Hardware Reset) states that the PHYRSTB pin must be asserted low > for at least 10ms (Tgap in Figure 10) and the system must wait at > minimum 30ms (for internal circuits settle time) before accessing > the PHY registers. Use 15ms and 35ms respectively to provide some > additional margin. > > [1] https://files.pine64.org/doc/datasheet/pine64/rtl8211e%28g%29-vb%28vl%29-cg_datasheet_1.6.pdf > > Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> i.e. will queue in renesas-devel for v7.4. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds