RE: [PATCH] arm64: dts: renesas: r9a08g045: Move max-frequency to SoC dtsi

Hi All,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: 19 June 2026 08:56
> Subject: [PATCH] arm64: dts: renesas: r9a08g045: Move max-frequency to SoC dtsi
> 
> From: Biju Das <[email protected]>
> 
> Move the max-frequency property for SDHI0/1/2 from the board-level SMARC dtsi files into the
> r9a08g045.dtsi SoC file, since these values reflect controller/SoC limitations rather than board-
> specific.
> 
> This removes the duplicated max-frequency = <125000000> entries for
> SDHI0 (both SD and eMMC variants) and SDHI1 in rzg3s-smarc-som.dtsi and rzg3s-smarc.dtsi, and the max-
> frequency = <50000000> entry for SDHI2, consolidating them as defaults in r9a08g045.dtsi instead.
> 
> Boards needing a different limit can still override max-frequency locally.
> 
> Signed-off-by: Biju Das <[email protected]>
> ---
>  arch/arm64/boot/dts/renesas/r9a08g045.dtsi       | 3 +++
>  arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 3 ---
>  arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi     | 1 -
>  3 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> index 3a69bb246bab..ae92d45ede38 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -655,6 +655,7 @@ sdhi0: mmc@11c00000  {
>  				 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
>  				 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
>  			clock-names = "core", "clkh", "cd", "aclk";
> +			max-frequency = <125000000>;
>  			resets = <&cpg R9A08G045_SDHI0_IXRST>;
>  			power-domains = <&cpg>;
>  			status = "disabled";
> @@ -670,6 +671,7 @@ sdhi1: mmc@11c10000 {
>  				 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
>  				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
>  			clock-names = "core", "clkh", "cd", "aclk";
> +			max-frequency = <125000000>;
>  			resets = <&cpg R9A08G045_SDHI1_IXRST>;
>  			power-domains = <&cpg>;
>  			status = "disabled";
> @@ -685,6 +687,7 @@ sdhi2: mmc@11c20000 {
>  				 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
>  				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
>  			clock-names = "core", "clkh", "cd", "aclk";
> +			max-frequency = <50000000>;
>  			resets = <&cpg R9A08G045_SDHI2_IXRST>;
>  			power-domains = <&cpg>;
>  			status = "disabled";
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-
> som.dtsi
> index b45acfe6288a..9039a927bc46 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -184,7 +184,6 @@ &sdhi0 {
>  	bus-width = <4>;
>  	sd-uhs-sdr50;
>  	sd-uhs-sdr104;
> -	max-frequency = <125000000>;
>  	status = "okay";
>  };
>  #else
> @@ -199,7 +198,6 @@ &sdhi0 {
>  	mmc-hs200-1_8v;
>  	non-removable;
>  	fixed-emmc-driver-type = <1>;
> -	max-frequency = <125000000>;
>  	status = "okay";
>  };
>  #endif
> @@ -210,7 +208,6 @@ &sdhi2 {
>  	pinctrl-names = "default";
>  	vmmc-supply = <&vcc_sdhi2>;
>  	bus-width = <4>;
> -	max-frequency = <50000000>;
>  	status = "okay";
>  };
>  #endif
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> index 70af605168b0..e3821d8c01e3 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> @@ -285,7 +285,6 @@ &sdhi1 {
>  	bus-width = <4>;
>  	sd-uhs-sdr50;
>  	sd-uhs-sdr104;
> -	max-frequency = <125000000>;
>  	status = "okay";
>  };
> 
> --
> 2.43.0

Gentle ping.

Cheers,
Biju