[PATCH v3 3/7] PCI: rzg3s-host: Drop nop instructions
Claudiu Beznea <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
From: Claudiu Beznea <[email protected]> On the RZ/G3S PCIe IP variant (which is similar to those used on the RZ/G3E, RZ/V2H, and RZ/V2N SoCs), access to the PCIe Type 1 registers requires setting the PCI_PERM.CFG_HWINIT_EN bit. Since this bit is not set on the code paths where rzg3s_pcie_set_max_link_speed() is called, the writes to PCI_EXP_LNKCTL2.TLS are nops. Drop them. Signed-off-by: Claudiu Beznea <[email protected]> --- Changes in v3: - none, this patch is new drivers/pci/controller/pcie-rzg3s-host.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index bbc5bcec03f1..3a28f5a15719 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1144,11 +1144,6 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) remote_supported_link_speeds != max_supported_link_speeds) return 0; - /* Set target Link speed */ - rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2, - PCI_EXP_LNKCTL2_TLS, - FIELD_PREP(PCI_EXP_LNKCTL2_TLS, link_speed)); - /* Request link speed change */ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, RZG3S_PCI_PCCTRL2_LS_CHG_REQ | -- 2.43.0