[PATCH 2/4] clk: renesas: r9a08g046: Add PCIe clocks and reset
Biju <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-clk,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> Add the PCIe module clocks (ACLK, CLKL1PM, CLK_PMU) and the PCIe reset signal for the RZ/G3L (R9A08G046) SoC, along with the P8 fixed clock required as the parent for CLKL1PM. Signed-off-by: Biju Das <[email protected]> --- drivers/clk/renesas/r9a08g046-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c index 5878423db151..22821321a1d3 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -335,6 +335,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = { dtable_8_256, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_FIXED("P8", R9A08G046_CLK_P8, CLK_PLL3_DIV2, 1, 8), DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_DIV_RSCI0_STS, dtable_2_16, 0, 100000000UL, 0, NULL), DEF_G3S_DIV("P14", R9A08G046_CLK_P14, CLK_SEL_RSCI1, G3L_DIV_RSCI1, G3L_DIV_RSCI1_STS, @@ -558,6 +559,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = { MSTOP(BUS_MCPU2, BIT(0))), DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))), + DEF_MOD("pci_aclk", R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0, + MSTOP(BUS_PERI_COM, BIT(10))), + DEF_MOD("pci_clkl1pm", R9A08G046_PCI_CLKL1PM, R9A08G046_CLK_P8, 0x608, 1, + MSTOP(BUS_PERI_COM, BIT(10))), + DEF_MOD("pci_clk_pmu", R9A08G046_PCI_CLK_PMU, R9A08G046_CLK_P1, 0x608, 2, + MSTOP(BUS_PERI_COM, BIT(10))), DEF_MOD("rsci0_pclk", R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0, MSTOP(BUS_MCPU2, BIT(7))), DEF_MOD("rsci1_pclk", R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1, @@ -633,6 +640,7 @@ static const struct rzg2l_reset r9a08g046_resets[] = { DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G046_PCI_ARESETN, 0x908, 0), DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0), DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1), DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2), @@ -671,6 +679,7 @@ static const unsigned int r9a08g046_no_pm_mod_clks[] = { MOD_CLK_BASE + R9A08G046_ETH1_CLK_RMII_I, MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I_RMII, MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I_RMII, + MOD_CLK_BASE + R9A08G046_PCI_CLKL1PM, }; const struct rzg2l_cpg_info r9a08g046_cpg_info = { -- 2.43.0