Re: [PATCH v7 6/9] dt-bindings: pwm: Document RZ/G3E GPT support
Biju Das <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,dev.linux.lists.sashiko-reviews,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-pwm |
|---|---|
| Message-ID | <CADT+UeBsPrADZdx34qS4YLyDwmO9Lq9qJMYWzhw0HW7+f_yZCQ@mail.gmail.com> |
Hello Sashiko, pwm.yaml already defines this property[1] as required. [1]https://elixir.bootlin.com/linux/v6.0-rc4/source/Documentation/devicetree/bindings/pwm/pwm.yaml#L23 On Mon, Aug 24, 2026 at 2:04 PM <[email protected]> wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] Add `#pwm-cells` to the `required` list. The binding omits this mandatory property for PWM providers. > -- > > --- Patch [6]: [PATCH v7 6/9] dt-bindings: pwm: Document RZ/G3E GPT support --- > commit 9a7d174b7aaab1e8640a8415696ce9830442c765 > Author: Biju Das <[email protected]> > > dt-bindings: pwm: Document RZ/G3E GPT support > > This commit documents the device tree bindings for the General PWM Timer > (GPT) on the Renesas RZ/G3E SoC. It details properties for the 16-channel > 32-bit timer, including interrupts, clocks, resets, and power domains. > > > diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml > > new file mode 100644 > > index 0000000000000..cb4ffab5f47fe > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml > > [ ... ] > > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-names > > + - clocks > > + - clock-names > > + - power-domains > > + - resets > > + - reset-names > > [Severity: Medium] > Since this hardware is a PWM provider and defines #pwm-cells in its > properties, should #pwm-cells be added to this required list? > > Leaving it out allows incomplete device tree nodes to pass schema validation. > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6