[PATCH v3 09/13] arm64: dts: renesas: r9a08g046: Add vspd node
Biju <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> Add vspd node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <[email protected]> --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index ad38aee2efb3..6ff145dc81fa 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -696,6 +696,20 @@ ssi3: ssi@100e4c00 { status = "disabled"; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a08g046-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg R9A08G046_LCDC_RESET_N>; + power-domains = <&cpg>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv"; reg = <0 0x10880000 0 0x10000>; -- 2.43.0