Re: [PATCH v3 03/13] drm: renesas: rzg2l_mipi_dsi: Move global timings into hardware info struct
Tommaso Merciai <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.freedesktop.lists.dri-devel,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <apAKnQLSjTP8tma8@tom-desktop> |
Hi Biju, Thanks for your patch. On Wed, Aug 26, 2026 at 06:48:37PM +0100, Biju wrote: > From: Biju Das <[email protected]> > > Move rzg2l_mipi_dsi_global_timings and its array size out of the hardcoded > ARRAY_SIZE reference in rzg2l_mipi_dsi_dphy_init() and into the struct > rzg2l_mipi_dsi_hw_info. This allows future hardware variants to supply > their own timing tables rather than sharing a single global array, making > the driver more extensible without code duplication. > > Signed-off-by: Biju Das <[email protected]> > --- > v2->v3: > * Dropped .dsi_global_timings from rzv2h_mipi_dsi_info as it uses > different path. Thanks for doing that. Patch LGTM now. Reviewed-by: Tommaso Merciai <[email protected]> Kind regards, Tommmaso > v1->v2: > * No change. > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 1538eeece2b5..d67e1230b70c 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -54,6 +54,8 @@ struct rzg2l_mipi_dsi_hw_info { > const u8 *table; > const u8 table_size; > } cpg_plldsi; > + const struct rzg2l_mipi_dsi_timings *dsi_global_timings; > + unsigned int num_dsi_global_timings; > u32 phy_reg_offset; > u32 link_reg_offset; > u32 dphyctrl0_init_val; > @@ -488,8 +490,8 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, > u32 dphytim3; > > /* All DSI global operation timings are set with recommended setting */ > - for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { > - dphy_timings = &rzg2l_mipi_dsi_global_timings[i]; > + for (i = 0; i < dsi->info->num_dsi_global_timings; ++i) { > + dphy_timings = &dsi->info->dsi_global_timings[i]; > if (hsfreq <= dphy_timings->hsfreq_max) > break; > } > @@ -1530,6 +1532,8 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { > .dphy_init = rzg2l_mipi_dsi_dphy_init, > .dphy_exit = rzg2l_mipi_dsi_dphy_exit, > .dphy_conf_clks = rzg2l_dphy_conf_clks, > + .dsi_global_timings = rzg2l_mipi_dsi_global_timings, > + .num_dsi_global_timings = ARRAY_SIZE(rzg2l_mipi_dsi_global_timings), > .link_reg_offset = 0x10000, > .dphyctrl0_init_val = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN | > DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR, > -- > 2.43.0 >