Re: [PATCH v3 11/13] arm64: dts: renesas: r9a08g046: Add LVDS node

On Wed, Aug 26, 2026 at 06:48:45PM +0100, Biju wrote:
> From: Biju Das <[email protected]>
> 
> Add LVDS node to RZ/G3L SoC DTSI.
>

Reviewed-by: Tommaso Merciai <[email protected]>

> Signed-off-by: Biju Das <[email protected]>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * No change.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 37 ++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index cc8bfb24da87..f652ad3f1d1a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -794,6 +794,43 @@ port@1 {
>  
>  				port@2 {
>  					reg = <2>;
> +					du_out_lvds: endpoint {
> +						remote-endpoint = <&lvds_in>;
> +					};
> +				};
> +			};
> +		};
> +
> +		lvds: lvds@108a0000 {
> +			compatible = "renesas,r9a08g046-lvds";
> +			reg = <0 0x108a0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> +				 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> +			clock-names = "pclk", "phyclk", "dotclk";
> +			resets = <&cpg R9A08G046_LVDS_RESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> +			reset-names = "lvdrst", "prst", "rst", "arst";
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					lvds_in: endpoint {
> +						remote-endpoint = <&du_out_lvds>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					lvds_out: endpoint {
> +					};
>  				};
>  			};
>  		};
> -- 
> 2.43.0
>