Re: [PATCH v4 12/15] rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Open-coded masking is still used in `rzn1_rtc_set_offset`, violating the commit's stated intent to replace them with the bitfield API.
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--- Patch [12]: [PATCH v4 12/15] rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access ---
commit ad6005d5cfeb80b3add21bb7f02da5fd44f8a3bd
Author: Lad Prabhakar <[email protected]>

rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access

This commit replaces open-coded shift and mask operations with the bitfield
API. It also updates the weekday field to an 8-bit definition to match the
hardware manual expectations.

> diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
> --- a/drivers/rtc/rtc-rzn1.c
> +++ b/drivers/rtc/rtc-rzn1.c

[ ... ]

> @@ -341,7 +347,7 @@ static int rzn1_rtc_set_offset(struct device *dev, long offset)
>  		subu |= steps + 1;
>  	} else {
>  		subu |= RZN1_RTC_SUBU_DECR;
> -		subu |= (~(-steps - 1)) & 0x3F;
> +		subu |= (~(-steps - 1)) & RZN1_RTC_SUBU_RTCA0FX;

[Severity: Low]
The commit message mentions replacing open-coded shift and mask operations
with the bitfield API.

In rzn1_rtc_set_offset(), this assignment uses the new macro but leaves the
masking operation open-coded.

Would it make sense to wrap this value with FIELD_PREP() to enforce the
compile-time checks and stay consistent with the rest of the patch?

>  	}
>  
>  	ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=12