Re: [PATCH v3 3/3] clk: samsung: exynos990: Fix PERIS gate clock parents

Hi Krysztof & Denzeel,

On Sat, 13 Jun 2026 at 13:36, Denzeel Oliva <[email protected]> wrote:
>
> Correct eight PERIS gate clock parents to match the hardware clock
> tree and reorder the GIC mux parents so mout_peris_bus_user is the
> default source.
>
> Signed-off-by: Denzeel Oliva <[email protected]>
> ---

Reviewed-by: Peter Griffin <[email protected]>

@Krysztof: I was thinking, maybe we should establish a new rule/best
practice for Samsung clock upstream submissions whereby patch
contributors should link to the downstream cal-if code for the SoC
after the --- line. That would make reviewing the patches' correctness
a bit easier, as the downstream cal-if code would be readily available
to the reviewer.

regards,

Peter

>  drivers/clk/samsung/clk-exynos990.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
> index ee3566b8e57c..df5928833b23 100644
> --- a/drivers/clk/samsung/clk-exynos990.c
> +++ b/drivers/clk/samsung/clk-exynos990.c
> @@ -2551,7 +2551,7 @@ static const unsigned long peris_clk_regs[] __initconst = {
>
>  /* Parent clock list for CMU_PERIS muxes */
>  PNAME(mout_peris_bus_user_p)           = { "oscclk", "mout_cmu_peris_bus" };
> -PNAME(mout_peris_clk_peris_gic_p)      = { "oscclk", "mout_peris_bus_user" };
> +PNAME(mout_peris_clk_peris_gic_p)      = { "mout_peris_bus_user", "oscclk" };
>
>  static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
>         MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
> @@ -2584,15 +2584,15 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
> -            "gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
> +            "gout_peris_clk_peris_oscclk_clk", "oscclk",
>              CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
> -            "gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
> +            "gout_peris_clk_peris_gic_clk", "mout_peris_clk_peris_gic",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
> -            "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
> +            "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_clk_peris_gic",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
>              21, CLK_IGNORE_UNUSED, 0),
>         GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
> @@ -2600,19 +2600,19 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_GIC_CLK,
> -            "gout_peris_gic_clk", "mout_peris_bus_user",
> +            "gout_peris_gic_clk", "mout_peris_clk_peris_gic",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
>              21, CLK_IS_CRITICAL, 0),
>         GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
> -            "gout_peris_lhm_axi_p_peris_clk", "oscclk",
> +            "gout_peris_lhm_axi_p_peris_clk", "mout_peris_bus_user",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
>              21, CLK_IGNORE_UNUSED, 0),
>         GATE(CLK_GOUT_PERIS_MCT_PCLK,
> -            "gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
> +            "gout_peris_mct_pclk", "mout_peris_bus_user",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
> -            "gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
> +            "gout_peris_otp_con_top_pclk", "mout_peris_bus_user",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
> @@ -2624,7 +2624,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
> -            "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
> +            "gout_peris_tmu_top_pclk", "mout_peris_bus_user",
>              CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
>              21, 0, 0),
>         GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,
>
> --
> 2.54.0
>