RE: [PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x

Hi Alexandru

> -----Original Message-----
> From: Alexandru Chimac <alex=40chimac.ro>
> Sent: Thursday, July 23, 2026 2:14 AM
> To: Krzysztof Kozlowski <krzk=40kernel.org>; Sylwester Nawrocki
> <s.nawrocki=40samsung.com>; Chanwoo Choi <cw00.choi=40samsung.com>;
> Peter Griffin <peter.griffin=40linaro.org>; Alim Akhtar
> <alim.akhtar=40samsung.com>; Michael Turquette
> <mturquette=40baylibre.com>; Stephen Boyd <sboyd=40kernel.org>; Brian
> Masney <bmasney=40redhat.com>; Rob Herring <robh=40kernel.org>; Conor
> Dooley <conor+dt=40kernel.org>; Alexandru Chimac <alex=40chimac.ro>;
> Krzysztof Kozlowski <krzk+dt=40kernel.org>
> Cc: linux-samsung-soc=40vger.kernel.org; linux-clk=40vger.kernel.org;
> devicetree=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; lin=
ux-
> kernel=40vger.kernel.org
> Subject: =5BPATCH v3 3/5=5D clk: samsung: clk-pll: Add support for pll_10=
61x
>=20
> These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and are simil=
ar
> to pll_1460x (using CON3 instead of CON1), so the code for that can handl=
e
> this PLL with a few small adaptations.
>=20
It is good to mention that PLL_1061x is a fractional type PLL and used to s=
upply BLK_MMC and AUD, atleast on 9610 SoC

> Signed-off-by: Alexandru Chimac <alex=40chimac.ro>
> ---
>  drivers/clk/samsung/clk-pll.c =7C 29 ++++++++++++++++++++++-------
> drivers/clk/samsung/clk-pll.h =7C  1 +
>  2 files changed, 23 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.=
c index
> e74552846ba3..2cda87235fa2 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> =40=40 -781,15 +781,20 =40=40 static unsigned long
> samsung_pll46xx_recalc_rate(struct clk_hw *hw,
>  	u64 fvco =3D parent_rate;
>=20
>  	pll_con0 =3D readl_relaxed(pll->con_reg);
> -	pll_con1 =3D readl_relaxed(pll->con_reg + 4);
> -	mdiv =3D (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type =3D=3D
> pll_1460x) ?
> +	if (pll->type =3D=3D pll_1061x)
> +		pll_con1 =3D readl_relaxed(pll->con_reg + 0xc);
Actually this is PLL_CON3 in UM, not suggesting to use a new variable but a=
 comment here will help.=20
Thanks=21