Re: [PATCH v2 6/8] arm64: dts: google: Align continued properties and add missing blank lines
Peter Griffin <[email protected]> Tue, 4 Aug 2026 13:11:28 +0100
| Newsgroups | org.kernel.vger.linux-samsung-soc,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <CADrjBPouUvFVLDWwDDS=+1EBfqSqUz1HLKcLPLRyjB++vBy88Q@mail.gmail.com> |
On Sat, 1 Aug 2026 at 16:07, Krzysztof Kozlowski <[email protected]> wrote: > > Trivial white-space only changes to adjust to DTS coding style and fix > dt-check-style strict warnings like: > > [required-blank-lines] child node must be preceded by a blank line > [continuation-alignment] continuation should align to column 39 (under = < or ") > > Reviewed-by: Andr=C3=A9 Draszik <[email protected]> > Signed-off-by: Krzysztof Kozlowski <[email protected]> > --- Reviewed-by: Peter Griffin <[email protected]> > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/bo= ot/dts/exynos/google/gs101.dtsi > index edc38f2d1183..bfceea5486f4 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -39,12 +39,15 @@ cluster0 { > core0 { > cpu =3D <&cpu0>; > }; > + > core1 { > cpu =3D <&cpu1>; > }; > + > core2 { > cpu =3D <&cpu2>; > }; > + > core3 { > cpu =3D <&cpu3>; > }; > @@ -54,6 +57,7 @@ cluster1 { > core0 { > cpu =3D <&cpu4>; > }; > + > core1 { > cpu =3D <&cpu5>; > }; > @@ -63,6 +67,7 @@ cluster2 { > core0 { > cpu =3D <&cpu6>; > }; > + > core1 { > cpu =3D <&cpu7>; > }; > @@ -1681,9 +1686,9 @@ usbdrd31: usb@11110000 { > compatible =3D "google,gs101-dwusb3"; > ranges =3D <0x0 0x11110000 0x10000>; > clocks =3D <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_= CLK_EARLY>, > - <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31= DRD_SUSPEND_CLK_26>, > - <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_A= CLK>, > - <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_P= CLK>; > + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB3= 1DRD_SUSPEND_CLK_26>, > + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_= ACLK>, > + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_= PCLK>; > clock-names =3D "bus_early", "susp_clk", "link_ac= lk", "link_pclk"; > #address-cells =3D <1>; > #size-cells =3D <1>; > > -- > 2.53.0 >