[PATCH v2 2/3] clk: samsung: clk-pll: Add support for pll_309
Aiden Isik via B4 Relay <[email protected]>
| Newsgroups | org.kernel.vger.linux-samsung-soc,org.infradead.lists.linux-arm-kernel,org.kernel.feeds.b4-sent,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-hardening,org.kernel.vger.linux-kernel |
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| Message-ID | <[email protected]> |
From: Aiden Isik <[email protected]> pll_309 (referred to in the downstream kernel sources as frd_309_rpll) is one of two PLLs used in the Exynos5515 SoC. It is an integer/fractional PLL with an FVCO of 600-2400MHz. It has the same locktime (500), and kdiv/mdiv/pdiv/sdiv masks and shifts as pll_531x, so it can be handled in exactly the same way. When defining a PLL, the "con" parameter should be set to the CON3 register, like this: PLL(pll_309, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), Signed-off-by: Aiden Isik <[email protected]> --- drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index e74552846ba3..73584fd1da5a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1728,6 +1728,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, break; case pll_531x: case pll_4311: + case pll_309: init.ops = &samsung_pll531x_clk_ops; break; case pll_1031x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index d6eb3246611b..2457cf47c109 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -53,6 +53,7 @@ enum samsung_pll_type { pll_1031x, pll_a9fracm, pll_a9fraco, + pll_309, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ -- 2.54.0