Re: [PATCH v4 02/10] mpi3mr: Update MPI Headers to revision 41
| Newsgroups | org.kernel.vger.linux-scsi |
|---|---|
| Message-ID | <[email protected]> |
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Incorrect shift macro definition `MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT` for mask `0x000c`. -- --- Patch [2]: [PATCH v4 02/10] mpi3mr: Update MPI Headers to revision 41 --- commit e227f986541dd8cdc45ad47d1ea7374c1b7cfc9c Author: Ranjan Kumar <[email protected]> mpi3mr: Update MPI Headers to revision 41 This commit updates the MPI headers to revision 41. > diff --git a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h > index 33dd303c97bb5..7cf16a5c15b72 100644 > --- a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h > +++ b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h [ ... ] > @@ -492,10 +498,31 @@ struct mpi3_man10_istwi_ctrlr_entry { > }; > > #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c) > -#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000) > -#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) > #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) > #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLITCH_FLTR_MASK (0xc000) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLITCH_FLTR_SHIFT (14) [ ... ] > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c) > +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) [Severity: Low] Is this shift value defined correctly? The mask MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK is defined as 0x000c, which covers bits 2 and 3. Should MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT be 2 instead of 0 to ensure any future bitwise operations work properly? -- Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2