[PATCH v12 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE SDHC nodes
Abhinaba Rakshit <[email protected]>
| Newsgroups | org.kernel.vger.linux-scsi,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-mmc |
|---|---|
| Message-ID | <20260824-enable-ice-clock-scaling-v12-5-09271f583dc6@oss.qualcomm.com> |
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE SDHC device nodes for Monaco platform. Signed-off-by: Abhinaba Rakshit <[email protected]> --- arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index ffb13d61ee36dca61bb4a720c51001fbbd135a40..91f55244078a9122365cba635f8d0034f70d11e0 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2742,6 +2742,27 @@ ice: crypto@1d88000 { clock-names = "core", "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; + + operating-points-v2 = <&ice_opp_table>; + + ice_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-201600000 { + opp-hz = /bits/ 64 <201600000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; crypto: crypto@1dfa000 { @@ -4907,6 +4928,22 @@ sdhc_ice: crypto@87c8000 { clock-names = "core", "iface"; power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&sdhc_ice_opp_table>; + + sdhc_ice_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; usb_1_hsphy: phy@8904000 { -- 2.34.1