Re: [PATCH v2] serial: 8250: handle ixp4xx register endianness correctly

On Thu, Jul 9, 2026, at 21:21, Linus Walleij wrote:
> From: Arnd Bergmann <[email protected]>
>
> Unlike modern SoCs that just work in both big-endian and little-endian
> mode using the readl()/writel() or readb()/writeb() accessors, the
> internal registers on ixp4xx behave like native-endian 32-bit registers
> in both modes, which requires adjusting the register address
> when using 8-bit access.
>
> The existing dts files are written for big-endian kernels and 8-bit
> access, which does not work with little-endian kernels.
>
> Add a quirk that makes the 8250 OF driver:
>
> 1. Mask off any hardcoded offset.
> 2. Add the += 3 offset if and only if we are running on big endian.
>
> This should work in all combinations of big-endian and little-endian
> kernels with either variant of the DTS file.
>
> Signed-off-by: Arnd Bergmann <[email protected]>
> [[email protected]: Modified to just play with the offset]
> Signed-off-by: Linus Walleij <[email protected]>
> ---
> Changes in v2:
> - Use PTR_ALIGN_DOWN(*,4) instead of the custom &= 3, which also
>   works with a pointer which is an unsigned char *
> - Fix to the earlycon code to do the same thing as the main
>   serial port.
> - Link to v1: 
> https://patch.msgid.link/[email protected]

Thanks a lot for the update, this looks good to me now.

It's barely worth keeping my authorship on it, as I'm sure
you have put more work into it than I did, but it's probably
not worth resending it just for that unless something else
comes up.

    Arnd