Re: [PATCH 2/2] serial: sc16is7xx: set TX FIFO trigger level to half FIFO to prevent underruns

Hi David,

> Does filling the tx buffer clear the IER bit?

No, filling the TX FIFO does not clear IER[1]. A THR write only clears the
pending TX interrupt condition/IRQ line, not the enable bit; for SPI this
is Fig. 33, "SPI write THR to clear TX interrupt".

During active TX, sc16is7xx_ier_set(THRI) is therefore just ensuring an
already-enabled interrupt remains enabled. It may be worth cleaning up
redundant updates later, but I would leave the current enable/disable policy
unchanged for the underrun fix.

> You might also be able to leave the tx interrupt permanently enabled.

THRI is already kept enabled during an active TX burst and is only cleared
by sc16is7xx_stop_tx() when the xmit FIFO becomes empty.

I think leaving it enabled while idle is a separate question. Since a THR
write clears the pending TX interrupt condition, an empty software FIFO means
there may be no write to clear a pending TX interrupt. With a level-low IRQ,
that could cause repeated wakeups while the hardware TX FIFO is empty.
So disabling IER[1] when the xmit FIFO is empty still looks like the right
policy. The cleanup I had in mind is only to avoid redundant 1->1 updates
while TX is already active.

> Did you try putting the second scope channel of the spi clock/data
> to get the scope to show you the pattern of transfers and the latencies?

Not yet. I scoped the RS-485 A/B output and the INT pin, while ftrace timed
the TXLVL read, FIFO write, and post-write TXLVL read separately. That was
enough to identify the stale-TXLVL under-fill. Capturing SCLK/SI/SO would
still be useful as an extra correlation check.

I am testing the re-read/top-up change now and want to get it validated on
another setup as well before sending v2. I will include the results in the
v2 cover letter.

Thanks
Paul