Re: [PATCH v2 09/10] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT

On Thu, Aug 06, 2026 at 05:34:17PM +0800, Long Zhao wrote:
> Enable the Ambarella ARMv8 platform Kconfig, add the CV75 SoC and
> EVK device trees, and select the Ambarella UART in the arm64
> defconfig for console bring-up.

Subject - missing dts prefix. Please do not come with your own style.
It's for example: arm64: dts: ambarella:


> 
> Signed-off-by: Long Zhao <[email protected]>
> ---
>  arch/arm64/Kconfig.platforms               |   9 ++
>  arch/arm64/boot/dts/Makefile               |   1 +
>  arch/arm64/boot/dts/ambarella/Makefile     |   3 +
>  arch/arm64/boot/dts/ambarella/cv75-evk.dts |  30 ++++++
>  arch/arm64/boot/dts/ambarella/cv75.dtsi    | 166 +++++++++++++++++++++++++++++
>  arch/arm64/configs/defconfig               |   3 +
>  6 files changed, 212 insertions(+)
> 
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index d2acfac73003..166430ddb3c9 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -26,6 +26,15 @@ config ARCH_SUNXI
>  	help
>  	  This enables support for Allwinner sunxi based SoCs like the A64.
>  
> +config ARCH_AMBARELLA
> +	bool "Ambarella SoC family"
> +	select ARM_PSCI
> +	select HAVE_ARM_ARCH_TIMER
> +	select PINCTRL
> +	select PINCTRL_AMB
> +	help
> +	  This enables support for the ARM64 based Ambarella SoCs like CV75.
> +
>  config ARCH_ALPINE
>  	bool "Annapurna Labs Alpine platform"
>  	select ALPINE_MSI if PCI
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index fc726b215f12..f1709eb5d915 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += airoha
>  subdir-y += allwinner
>  subdir-y += altera
>  subdir-y += amazon
> +subdir-y += ambarella
>  subdir-y += amd
>  subdir-y += amlogic
>  subdir-y += apm
> diff --git a/arch/arm64/boot/dts/ambarella/Makefile b/arch/arm64/boot/dts/ambarella/Makefile
> new file mode 100644
> index 000000000000..ddca3d7b18cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_AMBARELLA) += cv75-evk.dtb
> diff --git a/arch/arm64/boot/dts/ambarella/cv75-evk.dts b/arch/arm64/boot/dts/ambarella/cv75-evk.dts
> new file mode 100644
> index 000000000000..42a0fe24b83b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/cv75-evk.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Ambarella CV75 EVK board
> + */
> +
> +/dts-v1/;
> +
> +#include "cv75.dtsi"
> +
> +/ {
> +	model = "Ambarella CV75 EVK Board";
> +	compatible = "ambarella,cv75-evk", "ambarella,cv75";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart0;
> +	};
> +
> +	memory@200000 {
> +		device_type = "memory";
> +		reg = <0x0 0x00200000 0x0 0x07e00000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/ambarella/cv75.dtsi b/arch/arm64/boot/dts/ambarella/cv75.dtsi
> new file mode 100644
> index 000000000000..825b773f052f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/cv75.dtsi
> @@ -0,0 +1,166 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Ambarella CV75 SoC
> + *
> + * Boot peripheral: UART0 console.
> + * Clocks: a single ambarella,cv75-rct provider.
> + */
> +
> +#include <dt-bindings/clock/ambarella,cv75-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "ambarella,cv75";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	osc: oscillator {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-output-names = "osc";
> +		clock-frequency = <24000000>;
> +	};
> +
> +	psci {

This looks randomly ordered.

Please follow DTS coding style.


> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a76";
> +			device_type = "cpu";
> +			reg = <0x000>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a76";
> +			device_type = "cpu";
> +			reg = <0x100>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	gic: interrupt-controller@fff0101000 {

This cannot be here, it's MMIO node, you have dtbs check warnings
likely. Just look at any other file how it is done.

Please confirm that you have run dtbs_check W=1 and you fixed all the
warnings.

> +		compatible = "arm,gic-400";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		#size-cells = <1>;
> +		interrupt-controller;
> +		reg = <0xff 0xf0101000 0x0 0x1000>,
> +		      <0xff 0xf0102000 0x0 0x2000>,
> +		      <0xff 0xf0104000 0x0 0x2000>,
> +		      <0xff 0xf0106000 0x0 0x2000>;
> +		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* Clock provider and shared system registers. */
> +		rct: clock-controller@ffed080000 {
> +			compatible = "ambarella,cv75-rct", "syscon";
> +			reg = <0xff 0xed080000 0x0 0x1000>;
> +			clocks = <&osc>;
> +			clock-names = "osc";
> +			#clock-cells = <1>;
> +
> +			assigned-clocks = <&rct CV75_GCLK_UART0>;
> +			assigned-clock-parents = <&osc>;
> +			assigned-clock-rates = <24000000>;
> +		};
> +
> +		apb@ffe4000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xff 0xe4000000 0x0 0x01000000>;
> +			ranges = <0xe4000000 0xff 0xe4000000 0x01000000>;

You need to read DTS coding style.

Best regards,
Krzysztof