Fwd: [labor] 25/05/2004 04:02 security check output
Roman Garifullin <[email protected]> Tue, 25 May 2004 14:14:22 +0600
| Newsgroups | org.kernel.vger.linux-smp |
|---|---|
| Message-ID | <[email protected]> |
Hello, [email protected]. This log was received after unexpected rebooting system. I think, that You'll find this letter interesting. And may be, You'll answer me... Excuse me for my english, I am from Russia. ---------- The start of forwarded letter ---------- kernel log messages: > es: 262144 (order: 8, 1048576 bytes) > CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0 > CPU: L1 I cache: 12K, L1 D cache: 8K > CPU: L2 cache: 512K > CPU: Physical Processor ID: 0 > CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000 > Intel machine check architecture supported. > Intel machine check reporting enabled on CPU#0. > CPU: After generic, caps: bfebfbff 00000000 00000000 00000000 > CPU: Common caps: bfebfbff 00000000 00000000 00000000 > Enabling fast FPU save and restore... done. > Enabling unmasked SIMD FPU exception support... done. > Checking 'hlt' instruction... OK. > POSIX conformance testing by UNIFIX > mtrr: v1.40 (20010327) Richard Gooch ([email protected]) > mtrr: detected mtrr type: Intel > CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0 > CPU: L1 I cache: 12K, L1 D cache: 8K > CPU: L2 cache: 512K > CPU: Physical Processor ID: 0 > CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000 > Intel machine check reporting enabled on CPU#0. > CPU: After generic, caps: bfebfbff 00000000 00000000 00000000 > CPU: Common caps: bfebfbff 00000000 00000000 00000000 > CPU0: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07 > per-CPU timeslice cutoff: 1462.89 usecs. > task migration cache decay timeout: 10 msecs. > enabled ExtINT on CPU#0 > ESR value before enabling vector: 00000000 > ESR value after enabling vector: 00000000 > Booting processor 1/6 eip 2000 > Initializing CPU#1 > masked ExtINT on CPU#1 > ESR value before enabling vector: 00000000 > ESR value after enabling vector: 00000000 > Calibrating delay loop... 4784.12 BogoMIPS > CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0 > CPU: L1 I cache: 12K, L1 D cache: 8K > CPU: L2 cache: 512K > CPU: Physical Processor ID: 3 > CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000 > Intel machine check reporting enabled on CPU#1. > CPU: After generic, caps: bfebfbff 00000000 00000000 00000000 > CPU: Common caps: bfebfbff 00000000 00000000 00000000 > CPU1: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07 > Total of 2 processors activated (9555.14 BogoMIPS). > WARNING: No sibling found for CPU 0. > WARNING: No sibling found for CPU 1. > ENABLING IO-APIC IRQs > Setting 2 in the phys_id_present_map > ...changing IO-APIC physical APIC ID to 2 ... ok. > Setting 3 in the phys_id_present_map > ...changing IO-APIC physical APIC ID to 3 ... ok. > Setting 4 in the phys_id_present_map > ...changing IO-APIC physical APIC ID to 4 ... ok. > init IO_APIC IRQs > IO-APIC (apicid-pin) 2-0, 2-3, 2-5, 2-10, 2-11, 2-18, 2-22, 3-1, 3-2, 3-3, 3-4, 3-5, 3-6, 3-7, 3-8, 3-9, 3-10, 3-11, 3-12, 3-13, 3-14, 3-15, 3-16, 3-17, 3-18, 3-19, 3-20, 3-21, 3-22, 3-23, 4-0, 4-1, 4-2, 4-3, 4-4, 4-5, 4-6, 4-7, 4-8, 4-9, 4-10, 4-11, 4-12, 4-13, 4-14, 4-15, 4-16, 4-17, 4-18, 4-19, 4-20, 4-21, 4-22, 4-23 not connected. > ..TIMER: vector=0x31 pin1=2 pin2=0 > number of MP IRQ sources: 19. > number of IO-APIC #2 registers: 24. > number of IO-APIC #3 registers: 24. > number of IO-APIC #4 registers: 24. > testing the IO APIC....................... > > IO APIC #2...... > .... register #00: 02008000 > ....... : physical APIC id: 02 > WARNING: unexpected IO-APIC, please mail > to [email protected] > .... register #01: 00178020 > ....... : max redirection entries: 0017 > ....... : PRQ implemented: 1 > ....... : IO APIC version: 0020 > .... register #02: 00000000 > ....... : arbitration: 00 > .... IRQ redirection table: > NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect: > 00 000 00 1 0 0 0 0 0 0 00 > 01 003 03 0 0 0 0 0 1 1 39 > 02 003 03 0 0 0 0 0 1 1 31 > 03 000 00 1 0 0 0 0 0 0 00 > 04 003 03 0 0 0 0 0 1 1 41 > 05 000 00 1 0 0 0 0 0 0 00 > 06 003 03 0 0 0 0 0 1 1 49 > 07 003 03 0 0 0 0 0 1 1 51 > 08 003 03 0 0 0 0 0 1 1 59 > 09 003 03 0 0 0 0 0 1 1 61 > 0a 000 00 1 0 0 0 0 0 0 00 > 0b 000 00 1 0 0 0 0 0 0 00 > 0c 003 03 0 0 0 0 0 1 1 69 > 0d 003 03 0 0 0 0 0 1 1 71 > 0e 003 03 0 0 0 0 0 1 1 79 > 0f 003 03 0 0 0 0 0 1 1 81 > 10 003 03 1 1 0 1 0 1 1 89 > 11 003 03 1 1 0 1 0 1 1 91 > 12 000 00 1 0 0 0 0 0 0 00 > 13 003 03 1 1 0 1 0 1 1 99 > 14 003 03 1 1 0 1 0 1 1 A1 > 15 003 03 1 1 0 1 0 1 1 A9 > 16 000 00 1 0 0 0 0 0 0 00 > 17 003 03 1 1 0 1 0 1 1 B1 > > IO APIC #3...... > .... register #00: 03000000 > ....... : physical APIC id: 03 > .... register #01: 00178020 > ....... : max redirection entries: 0017 > ....... : PRQ implemented: 1 > ....... : IO APIC version: 0020 > .... register #02: 03000000 > ....... : arbitration: 03 > .... IRQ redirection table: > NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect: > 00 003 03 1 1 0 1 0 1 1 B9 > 01 000 00 1 0 0 0 0 0 0 00 > 02 000 00 1 0 0 0 0 0 0 00 > 03 000 00 1 0 0 0 0 0 0 00 > 04 000 00 1 0 0 0 0 0 0 00 > 05 000 00 1 0 0 0 0 0 0 00 > 06 000 00 1 0 0 0 0 0 0 00 > 07 000 00 1 0 0 0 0 0 0 00 > 08 000 00 1 0 0 0 0 0 0 00 > 09 000 00 1 0 0 0 0 0 0 00 > 0a 000 00 1 0 0 0 0 0 0 00 > 0b 000 00 1 0 0 0 0 0 0 00 > 0c 000 00 1 0 0 0 0 0 0 00 > 0d 000 00 1 0 0 0 0 0 0 00 > 0e 000 00 1 0 0 0 0 0 0 00 > 0f 000 00 1 0 0 0 0 0 0 00 > 10 000 00 1 0 0 0 0 0 0 00 > 11 000 00 1 0 0 0 0 0 0 00 > 12 000 00 1 0 0 0 0 0 0 00 > 13 000 00 1 0 0 0 0 0 0 00 > 14 000 00 1 0 0 0 0 0 0 00 > 15 000 00 1 0 0 0 0 0 0 00 > 16 000 00 1 0 0 0 0 0 0 00 > 17 000 00 1 0 0 0 0 0 0 00 > > IO APIC #4...... > .... register #00: 04000000 > ....... : physical APIC id: 04 > .... register #01: 00178020 > ....... : max redirection entries: 0017 > ....... : PRQ implemented: 1 > ....... : IO APIC version: 0020 > .... register #02: 04000000 > ....... : arbitration: 04 > .... IRQ redirection table: > NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect: > 00 000 00 1 0 0 0 0 0 0 00 > 01 000 00 1 0 0 0 0 0 0 00 > 02 000 00 1 0 0 0 0 0 0 00 > 03 000 00 1 0 0 0 0 0 0 00 > 04 000 00 1 0 0 0 0 0 0 00 > 05 000 00 1 0 0 0 0 0 0 00 > 06 000 00 1 0 0 0 0 0 0 00 > 07 000 00 1 0 0 0 0 0 0 00 > 08 000 00 1 0 0 0 0 0 0 00 > 09 000 00 1 0 0 0 0 0 0 00 > 0a 000 00 1 0 0 0 0 0 0 00 > 0b 000 00 1 0 0 0 0 0 0 00 > 0c 000 00 1 0 0 0 0 0 0 00 > 0d 000 00 1 0 0 0 0 0 0 00 > 0e 000 00 1 0 0 0 0 0 0 00 > 0f 000 00 1 0 0 0 0 0 0 00 > 10 000 00 1 0 0 0 0 0 0 00 > 11 000 00 1 0 0 0 0 0 0 00 > 12 000 00 1 0 0 0 0 0 0 00 > 13 000 00 1 0 0 0 0 0 0 00 > 14 000 00 1 0 0 0 0 0 0 00 > 15 000 00 1 0 0 0 0 0 0 00 > 16 000 00 1 0 0 0 0 0 0 00 > 17 000 00 1 0 0 0 0 0 0 00 > IRQ to pin mappings: > IRQ0 -> 0:2 > IRQ1 -> 0:1 > IRQ4 -> 0:4 > IRQ6 -> 0:6 > IRQ7 -> 0:7 > IRQ8 -> 0:8 > IRQ9 -> 0:9 > IRQ12 -> 0:12 > IRQ13 -> 0:13 > IRQ14 -> 0:14 > IRQ15 -> 0:15 > IRQ16 -> 0:16 > IRQ17 -> 0:17 > IRQ19 -> 0:19 > IRQ20 -> 0:20 > IRQ21 -> 0:21 > IRQ23 -> 0:23 > IRQ24 -> 1:0 > .................................... done. > Using local APIC timer interrupts. > calibrating APIC timer ... > ..... CPU clock speed is 2392.2730 MHz. > ..... host bus clock speed is 99.6779 MHz. > cpu: 0, clocks: 996779, slice: 332259 > CPU0<T0:996768,T1:664496,D:13,S:332259,C:996779> > cpu: 1, clocks: 996779, slice: 332259 > CPU1<T0:996768,T1:332240,D:10,S:332259,C:996779> > checking TSC synchronization across CPUs: passed. > PCI: PCI BIOS revision 2.10 entry at 0xfd921, last bus=5 > PCI: Using configuration type 1 >... ---------- The end of forwarded letter ---------- -- My best wishes, Roman mailto:[email protected]