Re: [PATCH v9 0/4] iommu/arm-smmu-v3: Tegra264 invalidation workaround
Will Deacon <[email protected]> Tue, 28 Jul 2026 12:15:24 +0100
| Newsgroups | org.kernel.vger.linux-tegra,dev.linux.lists.iommu,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-doc,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
On Sun, 26 Jul 2026 08:19:00 +0000, Ashish Mhetre wrote: > Nvidia Tegra264 SMMUs are affected by an erratum where a TLB entry can > survive an invalidation that races with concurrent traffic targeting > the same entry. The hardware-recommended software workaround is to > issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. > The second issue must execute only after the first issue's CMD_SYNC > has completed, giving the sequence: > > [...] Applied to iommu (arm/smmu/updates), thanks! But please check the comments from Sashiko if you get a chance: https://sashiko.dev/#/patchset/[email protected] [1/4] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions https://git.kernel.org/iommu/c/097bf4a02f2d [2/4] iommu/arm-smmu-v3: Add CFGI/TLBI-repeat workaround https://git.kernel.org/iommu/c/95ed2da20283 [3/4] iommu/arm-smmu-v3-iommufd: Report CFGI/TLBI-repeat erratum https://git.kernel.org/iommu/c/d501d66815ee [4/4] iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 https://git.kernel.org/iommu/c/06b15ddcfbc0 Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev