Re: [PATCH v9 5/5] arm64: tegra: Add PCIe root ports on Tegra264

Manivannan Sadhasivam <[email protected]> Wed, 5 Aug 2026 17:55:11 +0200

Newsgroups	org.kernel.vger.linux-tegra,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci
Message-ID	<y7bq45p7dmy7zoz3kpwqzr77kmjr6ce52vukjeec2yvpni4twc@ale6wgwp7eos>

On Wed, Aug 05, 2026 at 01:57:24PM +0200, Thierry Reding wrote:
> From: Thierry Reding <[email protected]>
> 
> The bindings have been updated to use the PCIe root port bindings, so
> the nodes for the root ports must be added.
> 
> Signed-off-by: Thierry Reding <[email protected]>
> ---
>  arch/arm64/boot/dts/nvidia/tegra264.dtsi | 66 +++++++++++++++++++++++++++++---
>  1 file changed, 60 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index cf9760c681b1..31bd29df8e46 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3562,10 +3562,19 @@ pci@c000000 {
>  			ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */
>  				 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
>  				 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
> -			bus-range = <0x0 0xff>;

bus-range for Host Bridge is still a valid property and the drivers are already
parsing it. Even though it usually pass the default values, I don't see a need
to remove it.

- Mani

-- 
மணிவண்ணன் சதாசிவம்