[PATCH v2 12/14] arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY
George Moussalem via B4 Relay <[email protected]>
| Newsgroups | org.kernel.vger.linux-usb,org.infradead.lists.linux-phy,org.kernel.feeds.b4-sent,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <[email protected]> |
From: Praveenkumar I <[email protected]> Enable USB Super-Speed PHY support. The PCIe and USB3 PHYs share the same MMIO address space, so override the compatible string to use the USB3 PHY driver instead of the PCIe PHY driver and set the required properties accordingly. Signed-off-by: Praveenkumar I <[email protected]> Signed-off-by: George Moussalem <[email protected]> --- arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index 25a70cd884c0..164f9a9a6c75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -100,3 +100,22 @@ &usbphy0 { status = "okay"; }; + +/* this combo PHY supports PCIe and USB3 */ +&pcie0_phy { + compatible = "qcom,ipq5018-uniphy-usb-ss-phy"; + + clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + + resets = <&gcc GCC_USB0_PHY_BCR>; + + qcom,phy-usb-mux-sel = <&tcsr 0x10540>; + + vdd-supply = <®ulator_fixed_5p0>; + + /delete-property/ num-lanes; + + status = "okay"; +}; -- 2.53.0