Re: [PATCH v2 7/7] soc: mediatek: mtk-mmsys: Add resets for mt8167

Krzysztof Kozlowski <[email protected]> Mon, 20 Jul 2026 08:30:31 +0200

Newsgroups	org.kernel.vger.linux-watchdog,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-mediatek,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel
Message-ID	<20260720-elegant-flawless-vole-aa3c1f@quoll>

On Fri, Jul 17, 2026 at 06:39:18PM +0200, Luca Leonardo Scorcia wrote:
> The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits
> registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as
> also stated in the downstream kernel for the Lenovo Smart Clock
> in the ddp_reg.h header.
> 
> Signed-off-by: Luca Leonardo Scorcia <[email protected]>
> ---
>  drivers/soc/mediatek/mt8167-mmsys.h | 41 +++++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c    |  3 +++
>  2 files changed, 44 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index eef14083c47b..dc3e882a9893 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -3,6 +3,47 @@
>  #ifndef __SOC_MEDIATEK_MT8167_MMSYS_H
>  #define __SOC_MEDIATEK_MT8167_MMSYS_H
>  
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <dt-bindings/reset/mediatek,mt8167-resets.h>
> +
> +#define MT8167_MMSYS_SW0_RST_B				0x140
> +#define MT8167_MMSYS_SW1_RST_B				0x144
> +
> +/* MMSYS resets */
> +static const u8 mmsys_mt8167_rst_tb[] = {

No, data structures NEVER go to the headers because it leads easily to
duplicated data.

Best regards,
Krzysztof