Re: [PATCH v3 5/8] dt-bindings: watchdog: renesas,r9a09g057-wdt: Add CPG/MSSR syscon support

On Thu, 16 Jul 2026 13:34:31 +0100, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
> 
> On the Renesas RZ/T2H SoC, the Watchdog Timer Control Register (WDTDCR)
> resides within the CPG/MSSR block rather than the WDT address space
> itself.
> 
> Previously, this was handled by including a second register range in the
> "reg" property. However, this is architecturally incorrect as the CPG/MSSR
> block consists of two distinct regions (0x80280000 and 0x81280000) that
> contain registers for multiple peripheral blocks.
> 
> Since the CPG/MSSR block is a multi-function block, introduce the
> "renesas,sysc" phandle-array property to allow the WDT driver to access
> its control register via this shared regmap.
> 
> Mark the use of a second "reg" entry as deprecated in favor of the
> new phandle-array approach for SoCs that require WDTDCR access.
> 
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v2->v3:
> - Updated property name to "renesas,sysc"
> - Updated description about deprecation and use of the new
>   phandle-array property.
> - Updated commit message
> 
> v1->v2:
> - No change.
> ---
>  .../watchdog/renesas,r9a09g057-wdt.yaml       | 29 +++++++++++++++++--
>  1 file changed, 27 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <[email protected]>