Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The new `samsung,exynos5515-wdt` conditional block may incorrectly enforce a 2-clock constraint, potentially violating the subsystem generation grouping rule.
--
--- Patch [1]: [PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible ---
commit 751ef37a6e709e26029d210213d732f6299f833b
Author: Aiden Isik <[email protected]>
dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
Add a dt-binding compatible for the Exynos5515 watchdog timer.
This watchdog requires a syscon phandle, and the cluster index should
*not* be specified, as that does not make sense on the Exynos5515 SoC
(due to it only having a single core cluster).
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 41aee1655b0c2..a32c478315779 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
[ ... ]
> @@ -93,6 +94,26 @@ allOf:
> - samsung,cluster-index
> - samsung,syscon-phandle
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - samsung,exynos5515-wdt
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Bus clock, used for register interface
> + - description: Source clock (driving watchdog counter)
> + clock-names:
> + items:
> + - const: watchdog
> + - const: watchdog_src
[Severity: Medium]
Does the Exynos 5515 hardware actually require two clocks?
Other Exynos 5 hardware, like the exynos5250 and exynos5420, typically
use a single clock constraint.
If the Exynos 5515 only has a single clock, this two-clock constraint will
unintentionally force device tree authors to provide a non-existent second
clock to pass schema validation.
> + samsung,cluster-index: false
> + required:
> + - samsung,syscon-phandle
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260818-for-next-lucky7-watchdog-v3-0-2912bd122c57@member.fsf.org?part=1
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