Re: [PATCH 01/20] dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC

On Fri, Aug 07, 2026 at 04:14:12PM +0530, Nagadheeraj Rottela wrote:
> From: Srinivas Neeli <[email protected]>
> 
> Add a binding for the Xilinx TSN Endpoint Ethernet MAC IP. The
> top-level node describes the IP wrapper, which owns the six shared
> IP clocks and the xlnx,num-priorities parameter, and has two
> children:
> 
>   - xlnx,tsn-ep-mac: the endpoint MAC, owning the host-side DMA
>     channels (dmas / dma-names / tx-queues-config).
> 
>   - xlnx,tsn-switch: the three-port Ethernet switch covering the
>     switch fabric and the two per-MAC register windows. The MDIO
>     controllers and PTP register blocks sit at fixed offsets inside
>     the per-MAC windows, accessed through the mdio-mac1 / mdio-mac2
>     children and per-MAC interrupt-names entries. Each external
>     port@N references its PHY through a phy-handle in the matching
>     mdio-mac<N> child.
> 
> Signed-off-by: Srinivas Neeli <[email protected]>
> Co-developed-by: Nagadheeraj Rottela <[email protected]>
> Signed-off-by: Nagadheeraj Rottela <[email protected]>
> ---
>  .../net/xlnx,tsn-endpoint-ethernet-mac.yaml   | 343 ++++++++++++++++++
>  MAINTAINERS                                   |   7 +
>  2 files changed, 350 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
> new file mode 100644
> index 000000000000..00f52b7b623c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
> @@ -0,0 +1,343 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/xlnx,tsn-endpoint-ethernet-mac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx TSN Endpoint Ethernet MAC
> +
> +description:
> +  TSN Endpoint Ethernet MAC IP implements IEEE 802.1 Time-Sensitive
> +  Networking (TSN) standards and provides low-latency network connectivity
> +  in either Endpoint-only or Bridged Endpoint configurations. In the
> +  Bridged Endpoint mode, the IP integrates a three-port switch, with two
> +  ports connected to the external network and one port connected to an
> +  internal endpoint. It also supports GMII/RGMII interfaces for connection
> +  to an external PHY, enabling full-duplex operation at 100 Mb/s and
> +  1 Gb/s speeds.
> +
> +maintainers:
> +  - Srinivas Neeli <[email protected]>
> +  - Nagadheeraj Rottela <[email protected]>
> +
> +properties:
> +  compatible:
> +    const: xlnx,tsn-endpoint-ethernet-mac-3.0
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: GTX clock for transmitter logic and RTC
> +      - description: GTX 90-degree phase shifted clock for RGMII
> +      - description: Host RX FIFO clock
> +      - description: Host TX FIFO clock
> +      - description: Reference clock for IDELAY control
> +      - description: AXI-Lite register interface clock
> +
> +  clock-names:
> +    items:
> +      - const: gtx
> +      - const: gtx90
> +      - const: host_rxfifo
> +      - const: host_txfifo
> +      - const: ref
> +      - const: s_axi
> +
> +  ranges: true
> +
> +  xlnx,num-priorities:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 2
> +    maximum: 8
> +    description:
> +      Number of traffic classes (priorities) configured in the IP.
> +      This is an IP configuration parameter that determines the number of
> +      priority queues available for QoS scheduling. Traffic classes map to
> +      IEEE 802.1Q priority levels (0-7).

Vendor specific properties go after standard properties. See ordering 
rules.

> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +patternProperties:
> +  "^ep-mac@":

'^ethernet@[0-9a-f]+$'

> +    type: object
> +    $ref: /schemas/net/ethernet-controller.yaml#

Move unevaluatedProperties here.

> +    description:
> +      Endpoint MAC sub-node. Provides the host-side data path through the
> +      DMA channels described by its dmas / dma-names.
> +    properties:
> +      compatible:
> +        const: xlnx,tsn-ep-mac
> +
> +      reg:
> +        maxItems: 1
> +
> +      dmas:
> +        minItems: 2
> +        maxItems: 32
> +
> +      dma-names:
> +        minItems: 2
> +        maxItems: 32
> +        items:
> +          pattern: "^(tx|rx)_chan(1[0-5]|[0-9])$"
> +        description: |
> +          Names matching the entries in 'dmas', one per DMA channel and in
> +          the same order. TX channel names use "tx_chan<N>" and RX channel
> +          names use "rx_chan<N>", where N is 0..15. Example: "tx_chan0",
> +          "tx_chan1", ..., "rx_chan0", "rx_chan1", ....
> +
> +      tx-queues-config:
> +        type: object

Move additionalProperties here.

> +        description:
> +          TX queue configuration node that maps IP priority queues to
> +          DMA TX channels. The TSN IP supports multiple priority queues for
> +          QoS scheduling, and each queue can be connected to a specific DMA
> +          channel. This mapping defines which DMA TX channel is used to
> +          transmit packets for each priority queue. For example, queue0
> +          with xlnx,dma-channel-num set to 5 means priority queue 0 uses
> +          tx_chan5 for data transfer.
> +
> +        patternProperties:
> +          "^queue[0-7]$":
> +            description:
> +              Each subnode represents a priority queue. The
> +              xlnx,dma-channel-num property specifies which DMA TX channel
> +              (tx_chan0 to tx_chan15) is connected to this queue for
> +              transmitting packets.
> +            type: object

Move additionalProperties here and then a blank line after.

> +            properties:
> +              xlnx,dma-channel-num:
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                description:
> +                  DMA TX channel number connected to this priority queue.
> +                minimum: 0
> +                maximum: 15
> +
> +            required:
> +              - xlnx,dma-channel-num
> +
> +            additionalProperties: false
> +
> +        additionalProperties: false
> +
> +    required:
> +      - compatible
> +      - reg
> +      - dmas
> +      - dma-names
> +      - tx-queues-config
> +
> +    unevaluatedProperties: false
> +
> +  "^switch@":

^switch@[0-9a-f]+$

> +    type: object
> +    $ref: /schemas/net/dsa/dsa.yaml#/$defs/ethernet-ports
> +    description:
> +      Three-port Ethernet switch sub-node. Contains the switch fabric
> +      register window and the two per-MAC register windows; each per-MAC
> +      window houses an MDIO controller and a PTP register block at fixed
> +      offsets. The IP's per-MAC and PTP-timer interrupts are exposed here.
> +
> +    properties:
> +      compatible:
> +        const: xlnx,tsn-switch
> +
> +      reg:
> +        items:
> +          - description: Switch fabric register window
> +          - description: MAC1 register window (includes MDIO and PTP)
> +          - description: MAC2 register window (includes MDIO and PTP)
> +
> +      reg-names:
> +        items:
> +          - const: switch
> +          - const: mac1
> +          - const: mac2
> +
> +      interrupts:
> +        maxItems: 7
> +
> +      interrupt-names:
> +        items:
> +          - const: ptp_rx_mac1
> +          - const: ptp_tx_mac1
> +          - const: mac_irq_mac1
> +          - const: ptp_timer
> +          - const: ptp_rx_mac2
> +          - const: ptp_tx_mac2
> +          - const: mac_irq_mac2
> +
> +      mdio-mac1:

mdio-1

> +        $ref: /schemas/net/mdio.yaml#
> +        description:
> +          MDIO bus controller for MAC1. Registers reside inside the mac1
> +          reg-names window.
> +        unevaluatedProperties: false
> +
> +      mdio-mac2:

mdio-2

> +        $ref: /schemas/net/mdio.yaml#
> +        description:
> +          MDIO bus controller for MAC2. Registers reside inside the mac2
> +          reg-names window.
> +        unevaluatedProperties: false
> +
> +      ethernet-ports:
> +        type: object
> +        additionalProperties: true
> +
> +        properties:
> +          port@0:
> +            type: object
> +            additionalProperties: true
> +            description:
> +              CPU port. Wired internally to the ep-mac sibling.
> +
> +            properties:
> +              reg:
> +                const: 0
> +
> +              phy-mode:
> +                const: internal
> +
> +        patternProperties:
> +          "^port@[1-2]$":
> +            type: object
> +            additionalProperties: true
> +            description:
> +              External Ethernet port (port@1 is wired to MAC1, port@2 to
> +              MAC2). Its PHY is reached through the corresponding
> +              mdio-mac<N> bus.
> +
> +            properties:
> +              phy-mode:
> +                enum:
> +                  - gmii
> +                  - rgmii
> +                  - rgmii-id
> +
> +    required:
> +      - compatible
> +      - reg
> +      - reg-names
> +      - interrupts
> +      - interrupt-names
> +
> +    unevaluatedProperties: false
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - xlnx,num-priorities
> +  - ranges
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +examples:
> +  - |
> +    tsn_ip: tsn@80040000 {

Drop unused labels.

Rob