Re: [PATCH net] net: txgbe: fix interrupt mask for MISC cause in non-MSI-X mode

On Thu, Aug 13, 2026 at 03:33:05PM +0800, Jiawen Wu wrote:
> In txgbe_misc_irq_thread_fn(), the driver unmasks the miscellaneous
> interrupt at the end of the handler using TXGBE_INTR_MISC(wx) (which
> resolves to BIT(wx->num_q_vectors)). While this is correct for MSI-X
> mode, it is incorrect for legacy INTx or single MSI modes.
> 
> Due to hardware behavior, the WX_PX_MISC_IVAR register is completely
> ignored by the hardware when MSI-X is disabled. In non-MSI-X mode, the
> hardware forcibly merges all interrupt causes (both Queue and MISC) into
> a single bit: BIT(0) of the interrupt register.
> 
> Unconditionally unmasking TXGBE_INTR_MISC(wx) (e.g., BIT(1)) in non-MSI-X
> mode means the actual MISC interrupt bit (BIT(0)) is not unmasked
> promptly at the end of the MISC thread. Instead, it remains masked until
> NAPI completes its polling and unmasks the shared BIT(0). This delays the
> assertion of subsequent MISC interrupts, preventing timely handling of
> events like link state changes.
> 
> Fix this by explicitly checking `pdev->msix_enabled` and falling back
> to BIT(0) as the interrupt mask for the MISC cause when MSI-X is disabled.
> 
> Fixes: e37546ad1f9b ("net: wangxun: revert the adjustment of the IRQ vector sequence")
> Signed-off-by: Jiawen Wu <[email protected]>

Reviewed-by: Simon Horman <[email protected]>