Re: [PATCH net v2] net: amd-xgbe: support receiving packets with bad FCS

On Wed, 19 Aug 2026 19:16:56 +1000
James <[email protected]> wrote:

> amd-xgbe driver currently sets the MAC_RCR.DCRCC bit whenever RX is
> enabled. This disables hardware FCS validation, causing packets with
> bad FCS to be accepted unconditionally.
> 
> This change unsets DCRCC so that packets with bad FCS will be dropped,
> in-line with typical behaviours of many other network controllers.
> 
> Tests:
> - Verified that packets with bad FCS are now dropped.
> - Verified that receiving packets with bad FCS will increment the
>   `rx_crc_errors` counter.
> 
> Signed-off-by: James Nugraha <[email protected]>
> ---
> Changes in v2:
> - Eliminated DCRCC toggling via RXALL: now it simply sets the
>   correct default value on MAC Rx enable
>  drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> index 2de974213..3ceb130a0 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> @@ -3400,7 +3400,7 @@ static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
>  	XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
>  
>  	/* Enable MAC Rx */
> -	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
> +	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
>  	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
>  	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
>  	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
> 

You can delete the line in the disable function that turns it off.

But, really, you should be setting the required MAC_RCR bits in a single
write.
Doing RMW sequences on the hardware registers for each bit is really wrong.
You also need to start with a known value for all the bits, otherwise
'silly' things can happen is (say) some bios boot code set bits you don't
otherwise change.

	David