[PATCH -perfbook v2 3/3] memorder: Update of ordering SSE non-temporal memory move instructions

Akira Yokosawa <[email protected]>
Newsgroups org.kernel.vger.perfbook
Message-ID <[email protected]>
Since Linux v4.15, smp_mb(), smp_wmb(), and smp_rmb() don't suffice
for ordering them.

Update the text accordingly and add a footnote.

Signed-off-by: Akira Yokosawa <[email protected]>
---
 memorder/memorder.tex | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 6b9c3268e589..da56a6999c3f 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -6075,8 +6075,10 @@ that same location, you are on your own.
 Some SSE instructions are weakly ordered (\co{clflush}
 and non-temporal move instructions~\cite{IntelXeonV2b-96a}).
 Code that uses these non-temporal move instructions
-can also use \co{mfence} for \co{smp_mb()},
-\co{lfence} for \co{smp_rmb()}, and \co{sfence} for \co{smp_wmb()}.
+can use \co{mfence} for \co{mb()},
+\co{lfence} for \co{rmb()}, and \co{sfence} for \co{wmb()}.\footnote{
+	\co{smp_mb()}, \co{smp_rmb()}, and \co{smp_wmb()} don't suffice
+	for ordering non-temporal move instructions since Linux v4.15.}
 A few older variants of the x86 CPU have a mode bit that enables out-of-order
 stores, and for these CPUs, \co{smp_wmb()} must also be defined to
 be \co{lock;addl}.
-- 
2.25.1
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