Re: [PATCH 1/2] arm64: dts: qcom: kodiak: Sort pinctrl subnodes by pins

On 6/12/26 3:46 PM, Luca Weiss wrote:
> On Fri Jun 12, 2026 at 2:59 PM CEST, Vladimir Zapolskiy wrote:
>> As documented in the "Devicetree Sources (DTS) Coding Style" document,
>> pinctrl subnodes should be sorted by the pins property. Do this once for
>> kodiak.dtsi so that future additions can be added at the right places.
>>
>> No functional change intended, verified with dtx_diff.
>>
>> Signed-off-by: Luca Weiss <[email protected]>
>> ---
>>   arch/arm64/boot/dts/qcom/kodiak.dtsi | 1382 +++++++++++++++++-----------------
>>   1 file changed, 691 insertions(+), 691 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> index fa540d8c2615..62daef726d32 100644
>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> 
> <snip>
> 
>> +			qup_uart12_cts: qup-uart12-cts-state {
>> +				pins = "gpio48";
>> +				function = "qup14";
>> +			};
>> +
>> +			qup_uart12_rts: qup-uart12-rts-state {
>> +				pins = "gpio49";
>> +				function = "qup14";
>> +			};
>> +
>> +			qup_uart12_tx: qup-uart12-tx-state {
>> +				pins = "gpio50";
>> +				function = "qup14";
>> +			};
>>
>> I understand and support the intention to keep this change non-functional,
>> but this pad "gpio50" is for qup16 also, right?
> 
> According to my QCM6490 data sheet, GPIO_50 has these functions:
> * UART for qup14 (OK)
> * SPI for qup14 (OK)
> * SPI for qup16 (no pinctrl)

"no pinctrl" meaning "not defined in the upstream dt as of today"?


> 
>>
>> Similarly pads "gpio54"/"gpio55" for qup14 function, "gpio62"/"gpio63"
>> for qup16 function, I find all of these are missing on the original list.
> 
> GPIO_54:
> * UART qup15 (OK)
> * SPI qup15 (OK)
> * SPI qup14 (no pinctrl)
> 
> GPIO_55:
> * UART qup15 (OK)
> * SPI qup15 (OK)
> * SPI qup14 (no pinctrl)
> 
> GPIO_62:
> * UART qup17 (OK)
> * SPI qup17 (OK)
> * SPI qup16 (no pinctrl)
> 
> GPIO_63:
> * UART qup16 (?)
> * SPI qup16 (lane 3) (?)
> * SPI qup16 (lane 5) (?)
> 
> But the GPIO_63 looks weird, is the data sheet wrong?! Where would
> UART_RX of QUP1 SE7 go? Maybe it should be UART qup17 and SPI qup17 and
> then SPI qup16 ??

GPIO63:

QUP1_SE6 SPI_CS2
QUP1_SE7 UART_RX/SPI_CS0

Konrad