[tip: x86/core] x86/locking: Use sfence for wmb() if SSE is available
"tip-bot2 for Yao Zi" <[email protected]>
| Newsgroups | org.kernel.vger.stable,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <178613330035.708.8011102097397557138.tip-bot2@tip-bot2> |
The following commit has been merged into the x86/core branch of tip: Commit-ID: d824ed1307680dd482f607b0e707c575f70668c4 Gitweb: https://git.kernel.org/tip/d824ed1307680dd482f607b0e707c575f70668c4 Author: Yao Zi <[email protected]> AuthorDate: Sat, 01 Aug 2026 18:29:53 Committer: Peter Zijlstra <[email protected]> CommitterDate: Fri, 07 Aug 2026 18:27:07 +02:00 x86/locking: Use sfence for wmb() if SSE is available When adding cc clobber to wmb()'s definition, the alternative() condition to use sfence was incorrectly raised from X86_FEATURE_XMM to X86_FEATURE_XMM2. Restore the correct constraint for potential better performance on machines without SSE2. Fixes: bd922477d935 ("locking/x86: Add cc clobber for ADDL") Signed-off-by: Yao Zi <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: [email protected] Link: https://patch.msgid.link/[email protected] --- arch/x86/include/asm/barrier.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index db70832..3e78bb7 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -17,7 +17,7 @@ #define rmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "lfence", \ X86_FEATURE_XMM2) ::: "memory", "cc") #define wmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "sfence", \ - X86_FEATURE_XMM2) ::: "memory", "cc") + X86_FEATURE_XMM) ::: "memory", "cc") #else #define __mb() asm volatile("mfence":::"memory") #define __rmb() asm volatile("lfence":::"memory")