[PATCH v5 01/15] iio: adc: xilinx-xadc: Correct Write edge in CFG
Dileep Kumar Nagavarapu <[email protected]>
| Newsgroups | org.kernel.vger.stable |
|---|---|
| Message-ID | <[email protected]> |
UG585 states about the PS-XADC interface configuration steps,
REDGE is 1 and WEDGE is 0, this is consistent with the XADCIF_CFG
register default value.
Configure WEDGE to 0 as specified by the TRM.Abnormal
XADC temperature readings observed on Zynq-7000 are no
longer reproducible with the documented setting applied.
Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver")
Cc: [email protected]
Signed-off-by: Conall O'Griofa <[email protected]>
Signed-off-by: Dileep Kumar Nagavarapu <[email protected]>
---
drivers/iio/adc/xilinx-xadc-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index cab66bb8cc1c..bfabe78b66e3 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -390,8 +390,7 @@ static int xadc_zynq_setup(struct platform_device *pdev,
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
- XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
- tck_div | XADC_ZYNQ_CFG_IGAP(igap));
+ XADC_ZYNQ_CFG_REDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
ret = clk_set_rate(xadc->clk, pcap_rate);
--
2.34.1